pie_code1111111.vhd

来自「pie edcode编码 程序设计」· VHDL 代码 · 共 64 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pie_code is
generic(--D : integer := 4;
		code_period : integer := 1250);

port(clk : in std_logic;
--	p : integer := 0;
	I : in std_logic;
	Q : out std_logic);
end pie_code;


architecture behave of pie_code is
--signal c : std_logic_vector(D downto 0);
signal j : integer range 0 to code_period-1 :=0 ;
signal k : integer range 0 to code_period-1 :=0 ;
--signal p : integer range 0 to 15 ;
begin
	process(clk)
	begin
		if clk'event and clk='1' then
			if (I='0' and j<code_period/2) then
				j<=j+1;
				Q<='1';
			elsif (I='0' and j>=code_period/2) then
				j<=j+1;
				Q<='0';
				if (j=code_period-1) then
					j<=0;
				end if;
			elsif (I='1' and j<code_period) then
				j<=j+1;
				Q<='1';
			elsif (I='1' and j=code_period-1 and k<code_period/2) then
				k<=k+1;
				Q<='1';
			elsif (I='1' and j=code_period-1 and k>=code_period/2) then
				k<=k+1;
				Q<='0';
				if (j=code_period-1) then
					j<=0;
				end if;	
				if (k=code_period-1) then
					k<=0;
				end if;	
				--c(D downto 1) <= (others=>'0');
				--c(0) <= '1';
				--Q <= c(D);
				--j<=0;
			
			--else
				--for i in 1 to D loop
				--	c(i) <= c(i-1);
				--end loop;
				
			end if;
		end if;
	end process;
end behave;