fff_nativelink.tcl

pie edcode编码 程序设计

## ================================================================================
## Legal Notice: Copyright (C) 1991-2006 Altera Corporation
## Any megafunction design, and related net list (encrypted or decrypted),
## support information, device programming or simulation file, and any other
## associated documentation or information provided by Altera or a partner
## under Altera's Megafunction Partnership Program may be used only to
## program PLD devices (but not masked PLD devices) from Altera.  Any other
## use of such megafunction design, net list, support information, device
## programming or simulation file, or any other related documentation or
## information is prohibited for any other purpose, including, but not
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## any other silicon devices, unless such use is explicitly licensed under
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## the intellectual property, including patents, copyrights, trademarks,
## trade secrets, or maskworks, embodied in any such megafunction design,
## net list, support information, device programming or simulation file, or
## any other related documentation or information provided by Altera or a
## megafunction partner, remains with Altera, the megafunction partner, or
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##


catch {set testbench_files [glob -nocomplain *.hex]} error_msg
puts "$error_msg"

# The top-level in HDL type "VHDL"
set ipfs_ext vho
if {[file exists fff.vho]} {
	set hdl_ext vhd
} else {
	puts "Warning: Could not find fff.$ipfs_ext!"
}

set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation

# Set test bench name
set_global_assignment -name EDA_TEST_BENCH_NAME tb -section_id eda_simulation


# test bench settings
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME fff_inst -section_id tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME fir_work.tb_fff -section_id tb

# IPFS file
set_global_assignment -name EDA_IPFS_FILE fff.$ipfs_ext -section_id eda_simulation -library fir_work

# Add Testbench files
foreach i $testbench_files {
  set_global_assignment -name EDA_TEST_BENCH_FILE $i -section_id tb -library fir_work
}

set_global_assignment -name EDA_TEST_BENCH_FILE fir_input.txt -section_id tb -library fir_work

set_global_assignment -name EDA_TEST_BENCH_FILE tb_fff.$hdl_ext -section_id tb -library fir_work

set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "1000 ns" -section_id tb -library fir_work

# Specify testbench mode for nativelink
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation

# Specify active testbench for nativelink
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb -section_id eda_simulation