fff_st_wr.v

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// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
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module fff_st_wr(clk, rst, clk_en, rdy_to_ld, done, data_in, fir_result);
parameter IN_WIDTH = 4;
parameter FACTOR = 2;
parameter OUT_WIDTH = 20;
parameter ACCUM_WIDTH = 20;
parameter COEF_SET_WIDTH = 1;
                                                                     
input  clk, rst;                                                     
input  clk_en;                                                     
input  [IN_WIDTH-1:0] data_in;                                     
output rdy_to_ld, done;                                           
output [OUT_WIDTH- 1:0] fir_result;                               
                                                                     
wire rdy_to_ld;                                                      
wire rdy_to_ld_int;                                                      
wire done;                                                           
wire rdy_out;                                                        
                                                                     
wire [OUT_WIDTH- 1:0] fir_result;                               
wire [OUT_WIDTH - 1:0] fir_int_res;                               
wire [COEF_SET_WIDTH - 1 :0] coef_set_cnt;                            
                                                                     
                                                                     
fff_st u0(.clk(clk),                                        
	    .rst(rst),                                                      
	    .clk_en(clk_en),                                                      
	    .data_in(data_in),                                              
	    .coef_set(coef_set_cnt),                                        
	    .done(done),                                                    
	    .rdy_to_ld(rdy_to_ld_int),                                          
	    .fir_result(fir_int_res)                                         
	    );                                                              
                                                                     
assign fir_result = fir_int_res;                            

mr_upc_wr u1(.clk(clk),                                            
		        .rst(rst),                                                      
		        .cen(rdy_to_ld_int & clk_en),                                                
		        .cnt_out(coef_set_cnt)                                          
		       );                                                              
defparam u1.SIZE = FACTOR;                                      
defparam u1.OUT_WIDTH = COEF_SET_WIDTH;                             
                                                                     
mr_lrdy_wr u2(.clk(clk),										
				 .rst(rst),                       
				 .clk_en(clk_en),   
				 .rdy_to_ld_int(rdy_to_ld_int),              
				 .done(done),              
				 .rdy_out(rdy_to_ld)              
				);            
					                                  
defparam u2.SIZE = FACTOR;                 
defparam u2.OUT_WIDTH = COEF_SET_WIDTH;    
defparam u2.CNT_VAL = 1;
                                                                     
endmodule													
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