tari_control.vhd

pie edcode编码 程序设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Tari_control is
generic(--D : integer := 4;
		code_period : integer := 1250);

port(clk : in std_logic;
--	p : integer := 0;
	I : in std_logic;
	Q : out std_logic);
end Tari_control;


architecture behave of Tari_control is
--signal c : std_logic_vector(D downto 0);
--signal j : integer range 0 to code_period*2-1 :=0 ;
--signal k : integer range 0 to code_period-1 :=0 ;
signal j : integer range 0 to 15 ;
begin
	process(clk)
	begin
		if clk'event and clk='1' then
		
			if (I='0' and j<code_period/2) then
				j<=j+1;
				Q<='1';
			elsif (I='0' and j>=code_period/2) then
				j<=j+1;
				Q<='0';
				if (j=code_period-1) then
					j<=0;
				end if;
			elsif (I='1' and j<code_period*3/2) then
				j<=j+1;
				Q<='1';
			elsif (I='1' and j>=code_period*3/2) then
				j<=j+1;
				Q<='0';
				if (j=code_period*2-1) then
					j<=0;
				end if;	
			end if;
			
		end if;
	end process;
end behave;