fff_st.v

pie edcode编码 程序设计

defparam Ur2_n_1_pp.CF =                  123;
assign lut_val_2_n_1_pp[15] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[14] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[13] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[12] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[11] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[10] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[9] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[8] = lut_val_2_n_1_pp[6];
assign lut_val_2_n_1_pp[7] = lut_val_2_n_1_pp[6];
wire [15:0] lut_val_3_n_0_pp;
rom_lut_r_cen Ur3_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[0],sym_res_18_n[0],sym_res_17_n[0],sym_res_15_n[0] } ), .data_out( lut_val_3_n_0_pp[9:0]) ) ;
 defparam Ur3_n_0_pp.DATA_WIDTH = 10;
defparam Ur3_n_0_pp.C0 =                    0;
defparam Ur3_n_0_pp.C1 =                   70;
defparam Ur3_n_0_pp.C2 =                  854;
defparam Ur3_n_0_pp.C3 =                  924;
defparam Ur3_n_0_pp.C4 =                  834;
defparam Ur3_n_0_pp.C5 =                  904;
defparam Ur3_n_0_pp.C6 =                  664;
defparam Ur3_n_0_pp.C7 =                  734;
defparam Ur3_n_0_pp.C8 =                  380;
defparam Ur3_n_0_pp.C9 =                  450;
defparam Ur3_n_0_pp.CA =                  210;
defparam Ur3_n_0_pp.CB =                  280;
defparam Ur3_n_0_pp.CC =                  190;
defparam Ur3_n_0_pp.CD =                  260;
defparam Ur3_n_0_pp.CE =                   20;
defparam Ur3_n_0_pp.CF =                   90;
assign lut_val_3_n_0_pp[15] = lut_val_3_n_0_pp[9];
assign lut_val_3_n_0_pp[14] = lut_val_3_n_0_pp[9];
assign lut_val_3_n_0_pp[13] = lut_val_3_n_0_pp[9];
assign lut_val_3_n_0_pp[12] = lut_val_3_n_0_pp[9];
assign lut_val_3_n_0_pp[11] = lut_val_3_n_0_pp[9];
assign lut_val_3_n_0_pp[10] = lut_val_3_n_0_pp[9];
wire [15:0] lut_val_3_n_1_pp;
rom_lut_r_cen Ur3_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_19_n[1],sym_res_18_n[1],sym_res_17_n[1],sym_res_15_n[1] } ), .data_out( lut_val_3_n_1_pp[9:0]) ) ;
 defparam Ur3_n_1_pp.DATA_WIDTH = 10;
defparam Ur3_n_1_pp.C0 =                    0;
defparam Ur3_n_1_pp.C1 =                   70;
defparam Ur3_n_1_pp.C2 =                  854;
defparam Ur3_n_1_pp.C3 =                  924;
defparam Ur3_n_1_pp.C4 =                  834;
defparam Ur3_n_1_pp.C5 =                  904;
defparam Ur3_n_1_pp.C6 =                  664;
defparam Ur3_n_1_pp.C7 =                  734;
defparam Ur3_n_1_pp.C8 =                  380;
defparam Ur3_n_1_pp.C9 =                  450;
defparam Ur3_n_1_pp.CA =                  210;
defparam Ur3_n_1_pp.CB =                  280;
defparam Ur3_n_1_pp.CC =                  190;
defparam Ur3_n_1_pp.CD =                  260;
defparam Ur3_n_1_pp.CE =                   20;
defparam Ur3_n_1_pp.CF =                   90;
assign lut_val_3_n_1_pp[15] = lut_val_3_n_1_pp[9];
assign lut_val_3_n_1_pp[14] = lut_val_3_n_1_pp[9];
assign lut_val_3_n_1_pp[13] = lut_val_3_n_1_pp[9];
assign lut_val_3_n_1_pp[12] = lut_val_3_n_1_pp[9];
assign lut_val_3_n_1_pp[11] = lut_val_3_n_1_pp[9];
assign lut_val_3_n_1_pp[10] = lut_val_3_n_1_pp[9];
wire [15:0] lut_val_4_n_0_pp;
rom_lut_r_cen Ur4_n_0_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[0],sym_res_22_n[0],sym_res_21_n[0],sym_res_20_n[0] } ), .data_out( lut_val_4_n_0_pp[15:0]) ) ;
 defparam Ur4_n_0_pp.DATA_WIDTH = 16;
defparam Ur4_n_0_pp.C0 =                    0;
defparam Ur4_n_0_pp.C1 =                 1881;
defparam Ur4_n_0_pp.C2 =                 4192;
defparam Ur4_n_0_pp.C3 =                 6073;
defparam Ur4_n_0_pp.C4 =                 6622;
defparam Ur4_n_0_pp.C5 =                 8503;
defparam Ur4_n_0_pp.C6 =                10814;
defparam Ur4_n_0_pp.C7 =                12695;
defparam Ur4_n_0_pp.C8 =                 8191;
defparam Ur4_n_0_pp.C9 =                10072;
defparam Ur4_n_0_pp.CA =                12383;
defparam Ur4_n_0_pp.CB =                14264;
defparam Ur4_n_0_pp.CC =                14813;
defparam Ur4_n_0_pp.CD =                16694;
defparam Ur4_n_0_pp.CE =                19005;
defparam Ur4_n_0_pp.CF =                20886;
wire [15:0] lut_val_4_n_1_pp;
rom_lut_r_cen Ur4_n_1_pp (.clk(clk),.gclk_en(clk_en),.addr_in( {sym_res_23_n[1],sym_res_22_n[1],sym_res_21_n[1],sym_res_20_n[1] } ), .data_out( lut_val_4_n_1_pp[15:0]) ) ;
 defparam Ur4_n_1_pp.DATA_WIDTH = 16;
defparam Ur4_n_1_pp.C0 =                    0;
defparam Ur4_n_1_pp.C1 =                 1881;
defparam Ur4_n_1_pp.C2 =                 4192;
defparam Ur4_n_1_pp.C3 =                 6073;
defparam Ur4_n_1_pp.C4 =                 6622;
defparam Ur4_n_1_pp.C5 =                 8503;
defparam Ur4_n_1_pp.C6 =                10814;
defparam Ur4_n_1_pp.C7 =                12695;
defparam Ur4_n_1_pp.C8 =                 8191;
defparam Ur4_n_1_pp.C9 =                10072;
defparam Ur4_n_1_pp.CA =                12383;
defparam Ur4_n_1_pp.CB =                14264;
defparam Ur4_n_1_pp.CC =                14813;
defparam Ur4_n_1_pp.CD =                16694;
defparam Ur4_n_1_pp.CE =                19005;
defparam Ur4_n_1_pp.CF =                20886;


// ---- partial product adder tree ----

wire [16:0] lut_0_bit_0_fill;
wire [16:0] lut_0_bit_1_fill;
assign lut_0_bit_0_fill = {lut_val_0_n_0_pp[15],  lut_val_0_n_0_pp };
assign lut_0_bit_1_fill = { lut_val_0_n_1_pp, 1'd0 };
wire [17:0] tree_0_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_0_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_0_bit_0_fill), .bin(lut_0_bit_1_fill), .res(tree_0_pp_l_0_n_0_n) );
defparam Uadd_0_lut_l_0_n_0_n.IN_WIDTH = 17;
defparam Uadd_0_lut_l_0_n_0_n.PIPE_DEPTH = 1;

wire [17:0] lut_val_0_n;
assign lut_val_0_n=tree_0_pp_l_0_n_0_n;


// ---- partial product adder tree ----

wire [16:0] lut_1_bit_0_fill;
wire [16:0] lut_1_bit_1_fill;
assign lut_1_bit_0_fill = {lut_val_1_n_0_pp[15],  lut_val_1_n_0_pp };
assign lut_1_bit_1_fill = { lut_val_1_n_1_pp, 1'd0 };
wire [17:0] tree_1_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_1_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_1_bit_0_fill), .bin(lut_1_bit_1_fill), .res(tree_1_pp_l_0_n_0_n) );
defparam Uadd_1_lut_l_0_n_0_n.IN_WIDTH = 17;
defparam Uadd_1_lut_l_0_n_0_n.PIPE_DEPTH = 1;

wire [17:0] lut_val_1_n;
assign lut_val_1_n=tree_1_pp_l_0_n_0_n;


// ---- partial product adder tree ----

wire [16:0] lut_2_bit_0_fill;
wire [16:0] lut_2_bit_1_fill;
assign lut_2_bit_0_fill = {lut_val_2_n_0_pp[15],  lut_val_2_n_0_pp };
assign lut_2_bit_1_fill = { lut_val_2_n_1_pp, 1'd0 };
wire [17:0] tree_2_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_2_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_2_bit_0_fill), .bin(lut_2_bit_1_fill), .res(tree_2_pp_l_0_n_0_n) );
defparam Uadd_2_lut_l_0_n_0_n.IN_WIDTH = 17;
defparam Uadd_2_lut_l_0_n_0_n.PIPE_DEPTH = 1;

wire [17:0] lut_val_2_n;
assign lut_val_2_n=tree_2_pp_l_0_n_0_n;


// ---- partial product adder tree ----

wire [16:0] lut_3_bit_0_fill;
wire [16:0] lut_3_bit_1_fill;
assign lut_3_bit_0_fill = {lut_val_3_n_0_pp[15],  lut_val_3_n_0_pp };
assign lut_3_bit_1_fill = { lut_val_3_n_1_pp, 1'd0 };
wire [17:0] tree_3_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_3_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_3_bit_0_fill), .bin(lut_3_bit_1_fill), .res(tree_3_pp_l_0_n_0_n) );
defparam Uadd_3_lut_l_0_n_0_n.IN_WIDTH = 17;
defparam Uadd_3_lut_l_0_n_0_n.PIPE_DEPTH = 1;

wire [17:0] lut_val_3_n;
assign lut_val_3_n=tree_3_pp_l_0_n_0_n;


// ---- partial product adder tree ----

wire [16:0] lut_4_bit_0_fill;
wire [16:0] lut_4_bit_1_fill;
assign lut_4_bit_0_fill = {lut_val_4_n_0_pp[15],  lut_val_4_n_0_pp };
assign lut_4_bit_1_fill = { lut_val_4_n_1_pp, 1'd0 };
wire [17:0] tree_4_pp_l_0_n_0_n;
sadd_lpm_cen Uadd_4_lut_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_4_bit_0_fill), .bin(lut_4_bit_1_fill), .res(tree_4_pp_l_0_n_0_n) );
defparam Uadd_4_lut_l_0_n_0_n.IN_WIDTH = 17;
defparam Uadd_4_lut_l_0_n_0_n.PIPE_DEPTH = 1;

wire [17:0] lut_val_4_n;
assign lut_val_4_n=tree_4_pp_l_0_n_0_n;


// ---- final adder tree ----

wire [18:0] fin_atree_l_0_n_0_n;
sadd_lpm_cen Uadd_cen_l_0_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_val_0_n), .bin(lut_val_1_n), .res(fin_atree_l_0_n_0_n) );
defparam Uadd_cen_l_0_n_0_n.IN_WIDTH = 18;
defparam Uadd_cen_l_0_n_0_n.PIPE_DEPTH = 1;
wire [18:0] fin_atree_l_0_n_1_n;
sadd_lpm_cen Uadd_cen_l_0_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_val_2_n), .bin(lut_val_3_n), .res(fin_atree_l_0_n_1_n) );
defparam Uadd_cen_l_0_n_1_n.IN_WIDTH = 18;
defparam Uadd_cen_l_0_n_1_n.PIPE_DEPTH = 1;
wire [18:0] fin_atree_l_0_n_2_n;
sadd_lpm_cen Uadd_cen_l_0_n_2_n (.clk(clk),  .gclk_en(clk_en), .ain(lut_val_4_n), .bin(18'd0), .res(fin_atree_l_0_n_2_n) );
defparam Uadd_cen_l_0_n_2_n.IN_WIDTH = 18;
defparam Uadd_cen_l_0_n_2_n.PIPE_DEPTH = 1;

wire [19:0] fin_atree_l_1_n_0_n;
sadd_lpm_cen Uadd_cen_l_1_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(fin_atree_l_0_n_0_n), .bin(fin_atree_l_0_n_1_n), .res(fin_atree_l_1_n_0_n) );
defparam Uadd_cen_l_1_n_0_n.IN_WIDTH = 19;
defparam Uadd_cen_l_1_n_0_n.PIPE_DEPTH = 1;
wire [19:0] fin_atree_l_1_n_1_n;
sadd_lpm_cen Uadd_cen_l_1_n_1_n (.clk(clk),  .gclk_en(clk_en), .ain(fin_atree_l_0_n_2_n), .bin(19'd0), .res(fin_atree_l_1_n_1_n) );
defparam Uadd_cen_l_1_n_1_n.IN_WIDTH = 19;
defparam Uadd_cen_l_1_n_1_n.PIPE_DEPTH = 1;

wire [20:0] fin_atree_l_2_n_0_n;
sadd_lpm_cen Uadd_cen_l_2_n_0_n (.clk(clk),  .gclk_en(clk_en), .ain(fin_atree_l_1_n_0_n), .bin(fin_atree_l_1_n_1_n), .res(fin_atree_l_2_n_0_n) );
defparam Uadd_cen_l_2_n_0_n.IN_WIDTH = 20;
defparam Uadd_cen_l_2_n_0_n.PIPE_DEPTH = 1;

wire [20:0] mac_res;
assign mac_res=fin_atree_l_2_n_0_n;
wire [20:0] atree_res;
mac_tl Umtl (.clk(clk), 
             .data_in(mac_res),
             .data_out(atree_res));
defparam Umtl.DATA_WIDTH = 21;

// ---- Adder Tree Complete ---- 
wire [16:0] fir_int_res;
assign fir_int_res = atree_res [16:0];

assign fir_result = fir_int_res[ACCUM_WIDTH-1:0];
wire pre_rdy;
assign rdy_to_ld = pre_rdy;
assign done = done_int;
par_ctrl Uctrl(.rst(rst),
		.clk(clk),
		.clk_en(clk_en),
		.done(done_int),
		.rdy_int(rdy_int),
		.rdy_to_ld(pre_rdy));
defparam Uctrl.REG_LEN = 7;
defparam Uctrl.REG_BIT = 3;
defparam Uctrl.CH_WIDTH =0; 
defparam Uctrl.NUM_CH =1; 
endmodule