fff_st.v

pie edcode编码 程序设计

// Generated by FIR Compiler
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2005 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera.  Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner.  Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors.  No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module fff_st (clk, 
              rst, 
              data_in, 
              clk_en, 
              rdy_to_ld, 
              done, 
              fir_result); 
parameter DATA_WIDTH  = 1;
parameter COEF_WIDTH  = 14;
parameter ACCUM_WIDTH = 17;

input clk, rst;
input [DATA_WIDTH-1:0] data_in;
input clk_en;
output rdy_to_ld;
wire rdy_to_ld;
wire rdy_int;
wire data_ld;
output done;
wire done;
wire done_int;
output [ACCUM_WIDTH-1:0] fir_result;
wire addr_low;
assign addr_low = 1'b0;


//--- Parallel TDL Storage ---
wire inv_rst;
assign inv_rst = ~rst;
assign data_ld = rdy_int;
wire [0:0] tdl_0_n;
wire [0:0] tdl_1_n;
wire [0:0] tdl_2_n;
wire [0:0] tdl_3_n;
wire [0:0] tdl_4_n;
wire [0:0] tdl_5_n;
wire [0:0] tdl_6_n;
wire [0:0] tdl_7_n;
wire [0:0] tdl_8_n;
wire [0:0] tdl_9_n;
wire [0:0] tdl_10_n;
wire [0:0] tdl_11_n;
wire [0:0] tdl_12_n;
wire [0:0] tdl_13_n;
wire [0:0] tdl_14_n;
wire [0:0] tdl_15_n;
wire [0:0] tdl_16_n;
wire [0:0] tdl_17_n;
wire [0:0] tdl_18_n;
wire [0:0] tdl_19_n;
wire [0:0] tdl_20_n;
wire [0:0] tdl_21_n;
wire [0:0] tdl_22_n;
wire [0:0] tdl_23_n;
wire [0:0] tdl_24_n;
wire [0:0] tdl_25_n;
wire [0:0] tdl_26_n;
wire [0:0] tdl_27_n;
wire [0:0] tdl_28_n;
wire [0:0] tdl_29_n;
wire [0:0] tdl_30_n;
wire [0:0] tdl_31_n;
wire [0:0] tdl_32_n;
wire [0:0] tdl_33_n;
wire [0:0] tdl_34_n;
wire [0:0] tdl_35_n;
wire [0:0] tdl_36_n;
wire [0:0] tdl_37_n;
wire [0:0] tdl_38_n;
wire [0:0] tdl_39_n;
wire [0:0] tdl_40_n;
wire [0:0] tdl_41_n;
wire [0:0] tdl_42_n;
wire [0:0] tdl_43_n;
wire [0:0] tdl_44_n;
wire [0:0] tdl_45_n;
wire [0:0] tdl_46_n;
wire [0:0] tdl_47_n;


//--- TDL  ---
tdl_da_lc Utdldalc0n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(data_in), .data_out(tdl_0_n) );
defparam Utdldalc0n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc1n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_0_n), .data_out(tdl_1_n) );
defparam Utdldalc1n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc2n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_1_n), .data_out(tdl_2_n) );
defparam Utdldalc2n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc3n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_2_n), .data_out(tdl_3_n) );
defparam Utdldalc3n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc4n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_3_n), .data_out(tdl_4_n) );
defparam Utdldalc4n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc5n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_4_n), .data_out(tdl_5_n) );
defparam Utdldalc5n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc6n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_5_n), .data_out(tdl_6_n) );
defparam Utdldalc6n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc7n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_6_n), .data_out(tdl_7_n) );
defparam Utdldalc7n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc8n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_7_n), .data_out(tdl_8_n) );
defparam Utdldalc8n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc9n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_8_n), .data_out(tdl_9_n) );
defparam Utdldalc9n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc10n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_9_n), .data_out(tdl_10_n) );
defparam Utdldalc10n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc11n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_10_n), .data_out(tdl_11_n) );
defparam Utdldalc11n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc12n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_11_n), .data_out(tdl_12_n) );
defparam Utdldalc12n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc13n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_12_n), .data_out(tdl_13_n) );
defparam Utdldalc13n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc14n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_13_n), .data_out(tdl_14_n) );
defparam Utdldalc14n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc15n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_14_n), .data_out(tdl_15_n) );
defparam Utdldalc15n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc16n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_15_n), .data_out(tdl_16_n) );
defparam Utdldalc16n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc17n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_16_n), .data_out(tdl_17_n) );
defparam Utdldalc17n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc18n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_17_n), .data_out(tdl_18_n) );
defparam Utdldalc18n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc19n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_18_n), .data_out(tdl_19_n) );
defparam Utdldalc19n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc20n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_19_n), .data_out(tdl_20_n) );
defparam Utdldalc20n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc21n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_20_n), .data_out(tdl_21_n) );
defparam Utdldalc21n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc22n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_21_n), .data_out(tdl_22_n) );
defparam Utdldalc22n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc23n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_22_n), .data_out(tdl_23_n) );
defparam Utdldalc23n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc24n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_23_n), .data_out(tdl_24_n) );
defparam Utdldalc24n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc25n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_24_n), .data_out(tdl_25_n) );
defparam Utdldalc25n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc26n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_25_n), .data_out(tdl_26_n) );
defparam Utdldalc26n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc27n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_26_n), .data_out(tdl_27_n) );
defparam Utdldalc27n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc28n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_27_n), .data_out(tdl_28_n) );
defparam Utdldalc28n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc29n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_28_n), .data_out(tdl_29_n) );
defparam Utdldalc29n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc30n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_29_n), .data_out(tdl_30_n) );
defparam Utdldalc30n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc31n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_30_n), .data_out(tdl_31_n) );
defparam Utdldalc31n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc32n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_31_n), .data_out(tdl_32_n) );
defparam Utdldalc32n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc33n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_32_n), .data_out(tdl_33_n) );
defparam Utdldalc33n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc34n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_33_n), .data_out(tdl_34_n) );
defparam Utdldalc34n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc35n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_34_n), .data_out(tdl_35_n) );
defparam Utdldalc35n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc36n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_35_n), .data_out(tdl_36_n) );
defparam Utdldalc36n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc37n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_36_n), .data_out(tdl_37_n) );
defparam Utdldalc37n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc38n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_37_n), .data_out(tdl_38_n) );
defparam Utdldalc38n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc39n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_38_n), .data_out(tdl_39_n) );
defparam Utdldalc39n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc40n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_39_n), .data_out(tdl_40_n) );
defparam Utdldalc40n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc41n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_40_n), .data_out(tdl_41_n) );
defparam Utdldalc41n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc42n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_41_n), .data_out(tdl_42_n) );
defparam Utdldalc42n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc43n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_42_n), .data_out(tdl_43_n) );
defparam Utdldalc43n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc44n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_43_n), .data_out(tdl_44_n) );
defparam Utdldalc44n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc45n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_44_n), .data_out(tdl_45_n) );
defparam Utdldalc45n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc46n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_45_n), .data_out(tdl_46_n) );
defparam Utdldalc46n.WIDTH = DATA_WIDTH;
tdl_da_lc Utdldalc47n (.clk(clk), .clk_en(rdy_int & clk_en),.rst(rst),.data_in(tdl_46_n), .data_out(tdl_47_n) );
defparam Utdldalc47n.WIDTH = DATA_WIDTH;


// --- ROM LUTs ---- 
// symmetrical adders ...
wire [1:0] sym_res_0_n;
uadd_cen U_0_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_0_n), .bin(tdl_47_n), .res(sym_res_0_n) );
defparam U_0_sym_add.IN_WIDTH = 1;
defparam U_0_sym_add.PIPE_DEPTH = 1;
wire [1:0] sym_res_1_n;
uadd_cen U_1_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_1_n), .bin(tdl_46_n), .res(sym_res_1_n) );
defparam U_1_sym_add.IN_WIDTH = 1;
defparam U_1_sym_add.PIPE_DEPTH = 1;
wire [1:0] sym_res_2_n;
uadd_cen U_2_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_2_n), .bin(tdl_45_n), .res(sym_res_2_n) );
defparam U_2_sym_add.IN_WIDTH = 1;
defparam U_2_sym_add.PIPE_DEPTH = 1;
wire [1:0] sym_res_3_n;
uadd_cen U_3_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_3_n), .bin(tdl_44_n), .res(sym_res_3_n) );
defparam U_3_sym_add.IN_WIDTH = 1;
defparam U_3_sym_add.PIPE_DEPTH = 1;
wire [1:0] sym_res_4_n;
uadd_cen U_4_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_4_n), .bin(tdl_43_n), .res(sym_res_4_n) );
defparam U_4_sym_add.IN_WIDTH = 1;
defparam U_4_sym_add.PIPE_DEPTH = 1;
wire [1:0] sym_res_5_n;
uadd_cen U_5_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_5_n), .bin(tdl_42_n), .res(sym_res_5_n) );
defparam U_5_sym_add.IN_WIDTH = 1;
defparam U_5_sym_add.PIPE_DEPTH = 1;
wire [1:0] sym_res_6_n;
uadd_cen U_6_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_6_n), .bin(tdl_41_n), .res(sym_res_6_n) );
defparam U_6_sym_add.IN_WIDTH = 1;
defparam U_6_sym_add.PIPE_DEPTH = 1;
wire [1:0] sym_res_7_n;
uadd_cen U_7_sym_add (.clk(clk), .gclk_en(clk_en), .ain(tdl_7_n), .bin(tdl_40_n), .res(sym_res_7_n) );