pie_code.tan.rpt

pie edcode编码 程序设计

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From                                                                                                                                                      ; To                                                                                                                                                                                                      ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; -0.092 ns                                      ; data_in                                                                                                                                                   ; fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]                                                                                                                 ; --         ; clock    ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 8.778 ns                                       ; fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_source:source|at_source_data[0]                                                                 ; data_out[0]                                                                                                                                                                                             ; clock      ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.340 ns                                       ; data_in                                                                                                                                                   ; fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|at_sink_data_int[0]                                                                                                                 ; --         ; clock    ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; Restricted to 195.01 MHz ( period = 5.128 ns ) ; fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|empty_dff ; fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|altsyncram_2lf1:FIFOram|ram_block1a0~portb_address_reg2 ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;                                                                                                                                                           ;                                                                                                                                                                                                         ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C35F672C7       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;