pie_code.fit.rpt

pie edcode编码 程序设计

; Optimize Timing                                        ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing             ; On                             ; On                             ;
; Limit to One Fitting Attempt                           ; Off                            ; Off                            ;
; Final Placement Optimizations                          ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations            ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                          ; 1                              ; 1                              ;
; PCI I/O                                                ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                  ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                              ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                     ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/III/Cyclone II/III ; Auto                           ; Auto                           ;
; Auto Delay Chains                                      ; On                             ; On                             ;
; Auto Merge PLLs                                        ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                      ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic     ; Off                            ; Off                            ;
; Perform Register Duplication                           ; Off                            ; Off                            ;
; Perform Register Retiming                              ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                 ; Off                            ; Off                            ;
; Fitter Effort                                          ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                        ; Normal                         ; Normal                         ;
; Auto Global Clock                                      ; On                             ; On                             ;
; Auto Global Register Control Signals                   ; On                             ; On                             ;
; Stop After Congestion Map Generation                   ; Off                            ; Off                            ;
; Use smart compilation                                  ; Off                            ; Off                            ;
+--------------------------------------------------------+--------------------------------+--------------------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in F:/program files/altera/61/qdesigns/my_work/pie_code/pie_code.pin.


+---------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                               ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                         ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------+
; Total logic elements                        ; 371 / 33,216 ( 1 % )                                                                          ;
;     -- Combinational with no register       ; 5                                                                                             ;
;     -- Register only                        ; 123                                                                                           ;
;     -- Combinational with a register        ; 243                                                                                           ;
;                                             ;                                                                                               ;
; Logic element usage by number of LUT inputs ;                                                                                               ;
;     -- 4 input functions                    ; 53                                                                                            ;
;     -- 3 input functions                    ; 128                                                                                           ;
;     -- <=2 input functions                  ; 67                                                                                            ;
;     -- Register only                        ; 123                                                                                           ;
;                                             ;                                                                                               ;
; Logic elements by mode                      ;                                                                                               ;
;     -- normal mode                          ; 156                                                                                           ;
;     -- arithmetic mode                      ; 92                                                                                            ;
;                                             ;                                                                                               ;
; Total registers*                            ; 366 / 34,593 ( 1 % )                                                                          ;
;     -- Dedicated logic registers            ; 366 / 33,216 ( 1 % )                                                                          ;
;     -- I/O registers                        ; 0 / 1,377 ( 0 % )                                                                             ;
;                                             ;                                                                                               ;
; Total LABs:  partially or completely used   ; 28 / 2,076 ( 1 % )                                                                            ;
; User inserted logic elements                ; 0                                                                                             ;
; Virtual pins                                ; 0                                                                                             ;
; I/O pins                                    ; 23 / 475 ( 5 % )                                                                              ;
;     -- Clock pins                           ; 2 / 8 ( 25 % )                                                                                ;
; Global signals                              ; 1                                                                                             ;
; M4Ks                                        ; 1 / 105 ( < 1 % )                                                                             ;
; Total memory bits                           ; 8 / 483,840 ( < 1 % )                                                                         ;
; Total RAM block bits                        ; 4,608 / 483,840 ( < 1 % )                                                                     ;
; Embedded Multiplier 9-bit elements          ; 0 / 70 ( 0 % )                                                                                ;
; PLLs                                        ; 0 / 4 ( 0 % )                                                                                 ;
; Global clocks                               ; 1 / 16 ( 6 % )                                                                                ;
; Average interconnect usage                  ; 0%                                                                                            ;
; Peak interconnect usage                     ; 2%                                                                                            ;
; Maximum fan-out node                        ; clock~clkctrl                                                                                 ;
; Maximum fan-out                             ; 367                                                                                           ;
; Highest non-global fan-out signal           ; fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_controller:intf_ctrl|sink_stall_reg ;
; Highest non-global fan-out                  ; 311                                                                                           ;
; Total fan-out                               ; 1929                                                                                          ;
; Average fan-out                             ; 2.62                                                                                          ;
+---------------------------------------------+-----------------------------------------------------------------------------------------------+
*  Register count does not include registers inside RAM blocks or DSP blocks.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                    ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name    ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clock   ; P2    ; 1        ; 0            ; 18           ; 2           ; 1                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
; data_in ; C13   ; 3        ; 31           ; 36           ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; 3.3-V LVTTL  ; Off         ; Fitter               ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+