pie_code.sim.rpt

来自「pie edcode编码 程序设计」· RPT 代码 · 共 252 行 · 第 1/5 页

; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      95.40 % ;
; Total nodes checked                                 ; 734          ;
; Total output ports checked                          ; 826          ;
; Total output ports with complete 1/0-value coverage ; 788          ;
; Total output ports with no 1/0-value coverage       ; 13           ;
; Total output ports with no 1-value coverage         ; 15           ;
; Total output ports with no 0-value coverage         ; 36           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                                                                                                                                                                                                                                         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                                                                                                                                             ; Output Port Name                                                                                                                                                                                         ; Output Port Type ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+
; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|counter_reg_bit3a[0] ; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|safe_q[0]               ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][16]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][16]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][15]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][15]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][14]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][14]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][13]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][13]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][12]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][12]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][11]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][11]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][10]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][10]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][9]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][9]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][8]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][8]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][7]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][7]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][6]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][6]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][5]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][5]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][4]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][4]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][3]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][3]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][2]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][2]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][1]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][1]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][0]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_2_n_0_n|pipe[0][0]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|counter_comb_bita0   ; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|counter_comb_bita0      ; combout          ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|counter_comb_bita0   ; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|counter_comb_bita0~COUT ; cout             ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|counter_comb_bita1   ; |pie_code|fff:inst1|fff_new:fff_new_inst|auk_dspip_avalon_streaming_sink:sink|scfifo:\normal_fifo:in_fifo|scfifo_ded1:auto_generated|a_dpfifo_i551:dpfifo|cntr_oj7:usedw_counter|counter_comb_bita1      ; combout          ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][16]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][16]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][12]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][12]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][11]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][11]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][10]                                                                                                  ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][10]                                                                                                     ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][9]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][9]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][8]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][8]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][7]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][7]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][6]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][6]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][5]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][5]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][4]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][4]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][3]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][3]                                                                                                      ; regout           ;
; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][2]                                                                                                   ; |pie_code|fff:inst1|fff_new:fff_new_inst|fff_st:fir_core|sadd_lpm_cen:Uadd_cen_l_1_n_0_n|pipe[0][2]                                                                                                      ; regout           ;