pie_code.eda.rpt

pie edcode编码 程序设计

EDA Netlist Writer report for pie_code
Tue Sep 11 09:59:46 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Board-Level Settings
  4. Board-Level Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; EDA Netlist Writer Summary                                                    ;
+---------------------------------------+---------------------------------------+
; EDA Netlist Writer Status             ; Successful - Tue Sep 11 09:59:46 2007 ;
; Revision Name                         ; pie_code                              ;
; Top-level Entity Name                 ; pie_code                              ;
; Family                                ; Cyclone II                            ;
; Board Signal Integrity Files Creation ; Successful                            ;
+---------------------------------------+---------------------------------------+


+-----------------------------------------+
; Board-Level Settings                    ;
+-------------------------------+---------+
; Option                        ; Setting ;
+-------------------------------+---------+
; Board Signal Integrity Format ; IBIS    ;
+-------------------------------+---------+


+----------------------------------------------------------------------------------+
; Board-Level Generated Files                                                      ;
+----------------------------------------------------------------------------------+
; Generated Files                                                                  ;
+----------------------------------------------------------------------------------+
; Board Signal Integrity                                                           ;
;     F:/program files/altera/61/qdesigns/my_work/pie_code/board/ibis/pie_code.ibs ;
+----------------------------------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
    Info: Processing started: Tue Sep 11 09:59:37 2007
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off pie_code -c pie_code
Info: Configuration pin models will be available in the next Quartus II release
Info: Generated IBIS Output File F:/program files/altera/61/qdesigns/my_work/pie_code/board/ibis/pie_code.ibs for board level analysis
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Allocated 166 megabytes of memory during processing
    Info: Processing ended: Tue Sep 11 09:59:46 2007
    Info: Elapsed time: 00:00:09