ppc405_top.vhd

PPC405 Lockstep System on ML310代码

  PPC405_i_0 : PPC405 port map (
    -- Clock and Power Management Interface / CPU Control Interface
    C405CPMCORESLEEPREQ        => C405CPMCORESLEEPREQ,           -- O
    C405CPMMSRCE               => C405CPMMSRCE,                  -- O 
    C405CPMMSREE               => C405CPMMSREE,                  -- O 
    C405CPMTIMERIRQ            => C405CPMTIMERIRQ,               -- O 
    C405CPMTIMERRESETREQ       => C405CPMTIMERRESETREQ,          -- O 
    C405XXXMACHINECHECK        => C405XXXMACHINECHECK,           -- O
    CPMC405CLOCK               => CPMC405CLOCK,                  -- I 
    CPMC405CORECLKINACTIVE     => CPMC405CORECLKINACTIVE,        -- I 
    CPMC405CPUCLKEN            => CPMC405CPUCLKEN,               -- I 
    CPMC405JTAGCLKEN           => CPMC405JTAGCLKEN,              -- I 
    CPMC405TIMERCLKEN          => CPMC405TIMERCLKEN,             -- I 
    CPMC405TIMERTICK           => CPMC405TIMERTICK,              -- I
    MCBCPUCLKEN                => MCBCPUCLKEN,                   -- I 
    MCBTIMEREN                 => MCBTIMEREN,                    -- I 
    MCPPCRST                   => MCPPCRST,                      -- I 
    PLBCLK                     => PLBCLK,                        -- I 
    TIEC405DETERMINISTICMULT   => DETERMINISTIC_MULT,            -- I
    TIEC405DISOPERANDFWD       => DISABLE_OPERAND_FORWARDING,    -- I
    TIEC405MMUEN               => MMU_ENABLE,                    -- I 
    -- Reset Interface
    C405RSTCHIPRESETREQ        => C405RSTCHIPRESETREQ,           -- O
    C405RSTCORERESETREQ        => C405RSTCORERESETREQ,           -- O
    C405RSTSYSRESETREQ         => C405RSTSYSRESETREQ,            -- O
    RSTC405RESETCHIP           => RSTC405RESETCHIP,              -- I
    RSTC405RESETCORE           => RSTC405RESETCORE,              -- I
    RSTC405RESETSYS            => RSTC405RESETSYS,               -- I
    -- Data Cache Unit PLB Interface
    C405PLBDCUABORT            => C405PLBDCUABORT,               -- O
    C405PLBDCUABUS             => C405PLBDCUABUS,                -- O [0:31]
    C405PLBDCUBE               => C405PLBDCUBE,                  -- O [0:7]
    C405PLBDCUCACHEABLE        => C405PLBDCUCACHEABLE,           -- O
    C405PLBDCUGUARDED          => C405PLBDCUGUARDED,             -- O
    C405PLBDCUPRIORITY         => C405PLBDCUPRIORITY,            -- O [0:1]
    C405PLBDCUREQUEST          => C405PLBDCUREQUEST,             -- O
    C405PLBDCURNW              => C405PLBDCURNW,                 -- O
    C405PLBDCUSIZE2            => DCU_PLB_SIZE2,                 -- O
    C405PLBDCUU0ATTR           => C405PLBDCUU0ATTR,              -- O
    C405PLBDCUWRDBUS           => C405PLBDCUWRDBUS,              -- O [0:63]
    C405PLBDCUWRITETHRU        => C405PLBDCUWRITETHRU,           -- O
    PLBC405DCUADDRACK          => PLBC405DCUADDRACK,             -- I
    PLBC405DCUBUSY             => PLBC405DCUBUSY,                -- I
    PLBC405DCUERR              => PLBC405DCUERR,                 -- I
    PLBC405DCURDDACK           => PLBC405DCURDDACK,              -- I
    PLBC405DCURDDBUS           => PLBC405DCURDDBUS,              -- I [0:63]
    PLBC405DCURDWDADDR         => DCU_PLB_MRdDBus,               -- I [1:3]
    PLBC405DCUSSIZE1           => DCU_PLB_MSSize,                -- I
    PLBC405DCUWRDACK           => PLBC405DCUWRDACK,              -- I
    -- Instruction Cache Unit PLB Interface
    C405PLBICUABORT            => C405PLBICUABORT,               -- O 
    C405PLBICUABUS             => ICU_PLB_ABus,                  -- O [0:29]
    C405PLBICUCACHEABLE        => C405PLBICUCACHEABLE,           -- O
    C405PLBICUPRIORITY         => C405PLBICUPRIORITY,            -- O [0:1]
    -- lockstep change
    C405PLBICUREQUEST          => C405PLBICUREQUEST_PPC_0,       -- O
    C405PLBICUSIZE             => ICU_PLB_SIZE,                  -- O [2:3]
    C405PLBICUU0ATTR           => C405PLBICUU0ATTR,              -- O 
    PLBC405ICUADDRACK          => PLBC405ICUADDRACK,             -- I 
    PLBC405ICUBUSY             => PLBC405ICUBUSY,                -- I 
    PLBC405ICUERR              => PLBC405ICUERR,                 -- I 
    PLBC405ICURDDACK           => PLBC405ICURDDACK,              -- I 
    PLBC405ICURDDBUS           => PLBC405ICURDDBUS,              -- I [0:63]
    PLBC405ICURDWDADDR         => ICU_PLB_MRdDBus,               -- I [1:3]
    PLBC405ICUSSIZE1           => ICU_PLB_MSSize,                -- I 
    -- Data Side XpressRAM Interface
    BRAMDSOCMCLK               => BRAMDSOCMCLK,                  -- I
    BRAMDSOCMRDDBUS            => BRAMDSOCMRDDBUS,               -- I [0:31]
    DSARCVALUE                 => DSARCVALUE,                    -- I [0:7]
    DSCNTLVALUE                => DSCNTLVALUE,                   -- I [0:7]
    DSOCMBRAMABUS              => DSOCMBRAMABUS,                 -- O [8:29]
    DSOCMBRAMBYTEWRITE         => DSOCMBRAMBYTEWRITE,            -- O [0:3]
    DSOCMBRAMEN                => DSOCMBRAMEN,                   -- O
    DSOCMBRAMWRDBUS            => DSOCMBRAMWRDBUS,               -- O [0:31]
    DSOCMBUSY                  => DSOCMBUSY,                     -- O
    TIEDSOCMDCRADDR            => C_DSOCM_DCR_BASEADDR(0 to 7),  -- I [0:7]
    -- Instruction Side XpressRAM Interface
    BRAMISOCMCLK               => BRAMISOCMCLK,                  -- I
    BRAMISOCMRDDBUS            => BRAMISOCMRDDBUS,               -- I [0:63]
    ISARCVALUE                 => ISARCVALUE,                    -- I [0:7]
    ISCNTLVALUE                => ISCNTLVALUE,                   -- I [0:7]
    ISOCMBRAMEN                => ISOCMBRAMEN,                   -- O
    ISOCMBRAMEVENWRITEEN       => ISOCMBRAMEVENWRITEEN,          -- O
    ISOCMBRAMODDWRITEEN        => ISOCMBRAMODDWRITEEN,           -- O
    ISOCMBRAMRDABUS            => ISOCMBRAMRDABUS,               -- O [0:28]
    ISOCMBRAMWRABUS            => ISOCMBRAMWRABUS,               -- O [8:28]
    ISOCMBRAMWRDBUS            => ISOCMBRAMWRDBUS,               -- O [0:31]
    TIEISOCMDCRADDR            => C_ISOCM_DCR_BASEADDR(0 to 7),  -- I [0:7]
    -- Device Control Register (DCR) Interface
    C405DCRABUS                => C405DCRABUS_E,                 -- O [0:9]
    C405DCRDBUSOUT             => C405DCRDBUSOUT_E,              -- O [0:31]
    C405DCRREAD                => C405DCRREAD_E,                 -- O
    C405DCRWRITE               => C405DCRWRITE_E,                -- O
    DCRC405ACK                 => DCRC405ACK_D,                  -- I
    DCRC405DBUSIN              => DCRC405DBUSIN_D,               -- I [0:31]
    -- Interrupt Controller Interface
    EICC405CRITINPUTIRQ        => EICC405CRITINPUTIRQ,           -- I
    EICC405EXTINPUTIRQ         => EICC405EXTINPUTIRQ,            -- I
    -- JTAG Interface
    C405JTGCAPTUREDR           => C405JTGCAPTUREDR,              -- O
    C405JTGEXTEST              => C405JTGEXTEST,                 -- O
    C405JTGPGMOUT              => C405JTGPGMOUT,                 -- O
    C405JTGSHIFTDR             => C405JTGSHIFTDR,                -- O
    -- lockstep changes
    C405JTGTDO                 => C405JTGTDO_PPC_0,              -- O
    C405JTGTDOEN               => C405JTGTDOEN_PPC_0,            -- O
    C405JTGUPDATEDR            => C405JTGUPDATEDR,               -- O
    MCBJTAGEN                  => MCBJTAGEN,                     -- I 
    JTGC405BNDSCANTDO          => JTGC405BNDSCANTDO,             -- I
    JTGC405TCK                 => JTGC405TCK,                    -- I
    JTGC405TDI                 => JTGC405TDI,                    -- I
    JTGC405TMS                 => JTGC405TMS,                    -- I
    JTGC405TRSTNEG             => JTGC405TRSTNEG,                -- I
    -- Debug Interface
    C405DBGMSRWE               => C405DBGMSRWE,                  -- O 
    C405DBGSTOPACK             => C405DBGSTOPACK,                -- O 
    C405DBGWBCOMPLETE          => C405DBGWBCOMPLETE,             -- O
    C405DBGWBFULL              => C405DBGWBFULL,                 -- O
    C405DBGWBIAR               => C405DBGWBIAR,                  -- O [0:29]
    DBGC405DEBUGHALT           => DBGC405DEBUGHALT,              -- I
    DBGC405EXTBUSHOLDACK       => DBGC405EXTBUSHOLDACK,          -- I
    DBGC405UNCONDDEBUGEVENT    => DBGC405UNCONDDEBUGEVENT,       -- I
    -- Trace Interface
    C405TRCCYCLE               => C405TRCCYCLE,                  -- O
    C405TRCEVENEXECUTIONSTATUS => C405TRCEVENEXECUTIONSTATUS,    -- O [0:1]
    C405TRCODDEXECUTIONSTATUS  => C405TRCODDEXECUTIONSTATUS,     -- O [0:1]
    C405TRCTRACESTATUS         => C405TRCTRACESTATUS,            -- O [0:3]
    C405TRCTRIGGEREVENTOUT     => C405TRCTRIGGEREVENTOUT,        -- O
    C405TRCTRIGGEREVENTTYPE    => C405TRCTRIGGEREVENTTYPE,       -- O [0:10]
    TRCC405TRACEDISABLE        => TRCC405TRACEDISABLE,           -- I
    TRCC405TRIGGEREVENTIN      => TRCC405TRIGGEREVENTIN          -- I
    );

  PPC405_i_1 : PPC405 port map (
    -- Clock and Power Management Interface / CPU Control Interface
    C405CPMCORESLEEPREQ        => open,
    C405CPMMSRCE               => open, 
    C405CPMMSREE               => open, 
    C405CPMTIMERIRQ            => open, 
    C405CPMTIMERRESETREQ       => open, 
    C405XXXMACHINECHECK        => open,
    CPMC405CLOCK               => CPMC405CLOCK,                  -- I 
    CPMC405CORECLKINACTIVE     => CPMC405CORECLKINACTIVE,        -- I 
    CPMC405CPUCLKEN            => CPMC405CPUCLKEN,               -- I 
    CPMC405JTAGCLKEN           => CPMC405JTAGCLKEN,              -- I 
    CPMC405TIMERCLKEN          => CPMC405TIMERCLKEN,             -- I 
    CPMC405TIMERTICK           => CPMC405TIMERTICK,              -- I
    MCBCPUCLKEN                => MCBCPUCLKEN,                   -- I 
    MCBTIMEREN                 => MCBTIMEREN,                    -- I 
    MCPPCRST                   => MCPPCRST,                      -- I 
    PLBCLK                     => PLBCLK,                        -- I 
    TIEC405DETERMINISTICMULT   => DETERMINISTIC_MULT,            -- I
    TIEC405DISOPERANDFWD       => DISABLE_OPERAND_FORWARDING,    -- I
    TIEC405MMUEN               => MMU_ENABLE,                    -- I 
    -- Reset Interface
    C405RSTCHIPRESETREQ        => open,
    C405RSTCORERESETREQ        => open,
    C405RSTSYSRESETREQ         => open,
    RSTC405RESETCHIP           => RSTC405RESETCHIP,              -- I
    RSTC405RESETCORE           => RSTC405RESETCORE,              -- I
    RSTC405RESETSYS            => RSTC405RESETSYS,               -- I
    -- Data Cache Unit PLB Interface
    C405PLBDCUABORT            => open,
    C405PLBDCUABUS             => open,
    C405PLBDCUBE               => open,
    C405PLBDCUCACHEABLE        => open,
    C405PLBDCUGUARDED          => open,
    C405PLBDCUPRIORITY         => open,
    C405PLBDCUREQUEST          => open,
    C405PLBDCURNW              => open,
    C405PLBDCUSIZE2            => open,
    C405PLBDCUU0ATTR           => open,
    C405PLBDCUWRDBUS           => open,
    C405PLBDCUWRITETHRU        => open,
    PLBC405DCUADDRACK          => PLBC405DCUADDRACK,             -- I
    PLBC405DCUBUSY             => PLBC405DCUBUSY,                -- I
    PLBC405DCUERR              => PLBC405DCUERR,                 -- I
    PLBC405DCURDDACK           => PLBC405DCURDDACK,              -- I
    PLBC405DCURDDBUS           => PLBC405DCURDDBUS,              -- I [0:63]
    PLBC405DCURDWDADDR         => DCU_PLB_MRdDBus,               -- I [1:3]
    PLBC405DCUSSIZE1           => DCU_PLB_MSSize,                -- I
    PLBC405DCUWRDACK           => PLBC405DCUWRDACK,              -- I
    -- Instruction Cache Unit PLB Interface
    C405PLBICUABORT            => open, 
    C405PLBICUABUS             => open,
    C405PLBICUCACHEABLE        => open,
    C405PLBICUPRIORITY         => open,
    -- lockstep change
    C405PLBICUREQUEST          => C405PLBICUREQUEST_PPC_1,       -- O
    C405PLBICUSIZE             => open,
    C405PLBICUU0ATTR           => open, 
    PLBC405ICUADDRACK          => PLBC405ICUADDRACK,             -- I 
    PLBC405ICUBUSY             => PLBC405ICUBUSY,                -- I 
    PLBC405ICUERR              => PLBC405ICUERR,                 -- I 
    PLBC405ICURDDACK           => PLBC405ICURDDACK,              -- I 
    PLBC405ICURDDBUS           => PLBC405ICURDDBUS,              -- I [0:63]
    PLBC405ICURDWDADDR         => ICU_PLB_MRdDBus,               -- I [1:3]
    PLBC405ICUSSIZE1           => ICU_PLB_MSSize,                -- I 
    -- Data Side XpressRAM Interface
    BRAMDSOCMCLK               => BRAMDSOCMCLK,                  -- I
    BRAMDSOCMRDDBUS            => BRAMDSOCMRDDBUS,               -- I [0:31]
    DSARCVALUE                 => DSARCVALUE,                    -- I [0:7]
    DSCNTLVALUE                => DSCNTLVALUE,                   -- I [0:7]
    DSOCMBRAMABUS              => open,
    DSOCMBRAMBYTEWRITE         => open,
    DSOCMBRAMEN                => open,
    DSOCMBRAMWRDBUS            => open,
    DSOCMBUSY                  => open,
    TIEDSOCMDCRADDR            => C_DSOCM_DCR_BASEADDR(0 to 7),  -- I [0:7]
    -- Instruction Side XpressRAM Interface
    BRAMISOCMCLK               => BRAMISOCMCLK,                  -- I
    BRAMISOCMRDDBUS            => BRAMISOCMRDDBUS,               -- I [0:63]
    ISARCVALUE                 => ISARCVALUE,                    -- I [0:7]
    ISCNTLVALUE                => ISCNTLVALUE,                   -- I [0:7]
    ISOCMBRAMEN                => open,
    ISOCMBRAMEVENWRITEEN       => open,
    ISOCMBRAMODDWRITEEN        => open,
    ISOCMBRAMRDABUS            => open,
    ISOCMBRAMWRABUS            => open,
    ISOCMBRAMWRDBUS            => open,
    TIEISOCMDCRADDR            => C_ISOCM_DCR_BASEADDR(0 to 7),  -- I [0:7]
    -- Device Control Register (DCR) Interface
    C405DCRABUS                => open,
    C405DCRDBUSOUT             => open,
    C405DCRREAD                => open,
    C405DCRWRITE               => open,
    DCRC405ACK                 => DCRC405ACK_D,                  -- I
    DCRC405DBUSIN              => DCRC405DBUSIN_D,               -- I [0:31]
    -- Interrupt Controller Interface
    EICC405CRITINPUTIRQ        => EICC405CRITINPUTIRQ,           -- I
    EICC405EXTINPUTIRQ         => EICC405EXTINPUTIRQ,            -- I
    -- JTAG Interface
    C405JTGCAPTUREDR           => open,
    C405JTGEXTEST              => open,
    C405JTGPGMOUT              => open,
    C405JTGSHIFTDR             => open,
    -- lockstep change
    C405JTGTDO                 => C405JTGTDO,                    -- O
    C405JTGTDOEN               => C405JTGTDOEN_PPC_1,            -- O
    C405JTGUPDATEDR            => open,
    MCBJTAGEN                  => MCBJTAGEN,                     -- I 
    JTGC405BNDSCANTDO          => JTGC405BNDSCANTDO,             -- I
    JTGC405TCK                 => JTGC405TCK,                    -- I
    JTGC405TDI                 => C405JTGTDO_PPC_0,              -- I
    JTGC405TMS                 => JTGC405TMS,                    -- I
    JTGC405TRSTNEG             => JTGC405TRSTNEG,                -- I
    -- Debug Interface
    C405DBGMSRWE               => open, 
    C405DBGSTOPACK             => open, 
    C405DBGWBCOMPLETE          => open,
    C405DBGWBFULL              => open,
    C405DBGWBIAR               => open,
    DBGC405DEBUGHALT           => DBGC405DEBUGHALT,              -- I
    DBGC405EXTBUSHOLDACK       => DBGC405EXTBUSHOLDACK,          -- I
    DBGC405UNCONDDEBUGEVENT    => DBGC405UNCONDDEBUGEVENT,       -- I
    -- Trace Interface
    C405TRCCYCLE               => open,
    C405TRCEVENEXECUTIONSTATUS => open,
    C405TRCODDEXECUTIONSTATUS  => open,
    C405TRCTRACESTATUS         => open,
    C405TRCTRIGGEREVENTOUT     => open,
    C405TRCTRIGGEREVENTTYPE    => open,
    TRCC405TRACEDISABLE        => TRCC405TRACEDISABLE,           -- I
    TRCC405TRIGGEREVENTIN      => TRCC405TRIGGEREVENTIN          -- I
    );

end structure;