ppc405_top.vhd

PPC405 Lockstep System on ML310代码

      TIEC405DETERMINISTICMULT : in  std_logic;
      TIEC405DISOPERANDFWD     : in  std_logic;
      TIEC405MMUEN             : in  std_logic;

      -- Reset Interface
      C405RSTCHIPRESETREQ : out std_logic;
      C405RSTCORERESETREQ : out std_logic;
      C405RSTSYSRESETREQ  : out std_logic;
      RSTC405RESETCHIP    : in  std_logic;
      RSTC405RESETCORE    : in  std_logic;
      RSTC405RESETSYS     : in  std_logic;

      -- Data Cache Unit PLB Interface
      C405PLBDCUABORT     : out std_logic;
      C405PLBDCUABUS      : out std_logic_vector(0 to 31);
      C405PLBDCUBE        : out std_logic_vector(0 to 7);
      C405PLBDCUCACHEABLE : out std_logic;
      C405PLBDCUGUARDED   : out std_logic;
      C405PLBDCUPRIORITY  : out std_logic_vector(0 to 1);
      C405PLBDCUREQUEST   : out std_logic;
      C405PLBDCURNW       : out std_logic;
      C405PLBDCUSIZE2     : out std_logic;
      C405PLBDCUU0ATTR    : out std_logic;
      C405PLBDCUWRDBUS    : out std_logic_vector(0 to 63);
      C405PLBDCUWRITETHRU : out std_logic;
      PLBC405DCUADDRACK   : in  std_logic;
      PLBC405DCUBUSY      : in  std_logic;
      PLBC405DCUERR       : in  std_logic;
      PLBC405DCURDDACK    : in  std_logic;
      PLBC405DCURDDBUS    : in  std_logic_vector(0 to 63);
      PLBC405DCURDWDADDR  : in  std_logic_vector(1 to 3);
      PLBC405DCUSSIZE1    : in  std_logic;
      PLBC405DCUWRDACK    : in  std_logic;

      -- Instruction Cache Unit PLB Interface
      C405PLBICUABORT     : out std_logic;
      C405PLBICUABUS      : out std_logic_vector(0 to 29);
      C405PLBICUCACHEABLE : out std_logic;
      C405PLBICUPRIORITY  : out std_logic_vector(0 to 1);
      C405PLBICUREQUEST   : out std_logic;
      C405PLBICUSIZE      : out std_logic_vector(2 to 3);
      C405PLBICUU0ATTR    : out std_logic;
      PLBC405ICUADDRACK   : in  std_logic;
      PLBC405ICUBUSY      : in  std_logic;
      PLBC405ICUERR       : in  std_logic;
      PLBC405ICURDDACK    : in  std_logic;
      PLBC405ICURDDBUS    : in  std_logic_vector(0 to 63);
      PLBC405ICURDWDADDR  : in  std_logic_vector(1 to 3);
      PLBC405ICUSSIZE1    : in  std_logic;

      -- Data Side XpressRAM Interface
      BRAMDSOCMCLK       : in  std_logic;
      BRAMDSOCMRDDBUS    : in  std_logic_vector(0 to 31);
      DSARCVALUE         : in  std_logic_vector(0 to 7);
      DSCNTLVALUE        : in  std_logic_vector(0 to 7);
      DSOCMBRAMABUS      : out std_logic_vector(8 to 29);
      DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3);
      DSOCMBRAMEN        : out std_logic;
      DSOCMBRAMWRDBUS    : out std_logic_vector(0 to 31);
      DSOCMBUSY          : out std_logic;
      TIEDSOCMDCRADDR    : in  std_logic_vector(0 to 7);

      -- Instruction Side XpressRAM Interface
      BRAMISOCMCLK         : in  std_logic;
      BRAMISOCMRDDBUS      : in  std_logic_vector(0 to 63);
      ISARCVALUE           : in  std_logic_vector(0 to 7);
      ISCNTLVALUE          : in  std_logic_vector(0 to 7);
      ISOCMBRAMEN          : out std_logic;
      ISOCMBRAMEVENWRITEEN : out std_logic;
      ISOCMBRAMODDWRITEEN  : out std_logic;
      ISOCMBRAMRDABUS      : out std_logic_vector(8 to 28);
      ISOCMBRAMWRABUS      : out std_logic_vector(8 to 28);
      ISOCMBRAMWRDBUS      : out std_logic_vector(0 to 31);
      TIEISOCMDCRADDR      : in  std_logic_vector(0 to 7);

      -- Device Control Register (DCR) Interface
      C405DCRABUS    : out std_logic_vector(0 to 9);
      C405DCRDBUSOUT : out std_logic_vector(0 to 31);
      C405DCRREAD    : out std_logic;
      C405DCRWRITE   : out std_logic;
      DCRC405ACK     : in  std_logic;
      DCRC405DBUSIN  : in  std_logic_vector(0 to 31);

      -- Interrupt Controller Interface
      EICC405CRITINPUTIRQ : in std_logic;
      EICC405EXTINPUTIRQ  : in std_logic;

      -- JTAG Interface
      C405JTGCAPTUREDR  : out std_logic;
      C405JTGEXTEST     : out std_logic;
      C405JTGPGMOUT     : out std_logic;
      C405JTGSHIFTDR    : out std_logic;
      C405JTGTDO        : out std_logic;
      C405JTGTDOEN      : out std_logic;
      C405JTGUPDATEDR   : out std_logic;
      MCBJTAGEN         : in  std_logic;
      JTGC405BNDSCANTDO : in  std_logic;
      JTGC405TCK        : in  std_logic;
      JTGC405TDI        : in  std_logic;
      JTGC405TMS        : in  std_logic;
      JTGC405TRSTNEG    : in  std_logic;

      -- Debug Interface
      C405DBGMSRWE            : out std_logic;
      C405DBGSTOPACK          : out std_logic;
      C405DBGWBCOMPLETE       : out std_logic;
      C405DBGWBFULL           : out std_logic;
      C405DBGWBIAR            : out std_logic_vector(0 to 29);
      DBGC405DEBUGHALT        : in  std_logic;
      DBGC405EXTBUSHOLDACK    : in  std_logic;
      DBGC405UNCONDDEBUGEVENT : in  std_logic;

      -- Trace Interface
      C405TRCCYCLE               : out std_logic;
      C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1);
      C405TRCODDEXECUTIONSTATUS  : out std_logic_vector(0 to 1);
      C405TRCTRACESTATUS         : out std_logic_vector(0 to 3);
      C405TRCTRIGGEREVENTOUT     : out std_logic;
      C405TRCTRIGGEREVENTTYPE    : out std_logic_vector(0 to 10);
      TRCC405TRACEDISABLE        : in  std_logic;
      TRCC405TRIGGEREVENTIN      : in  std_logic
      );
  end component;

----------------------------------------------------------------------------
-- Signal Declarations
----------------------------------------------------------------------------
  signal ICU_PLB_ABus    : std_logic_vector(0 to 29);
  signal ICU_PLB_SIZE    : std_logic_vector(2 to 3);
  signal ICU_PLB_MRdDBus : std_logic_vector(1 to 3);
  signal ICU_PLB_MSSize  : std_logic;

  signal DCU_PLB_SIZE2   : std_logic;
  signal DCU_PLB_MRdDBus : std_logic_vector(1 to 3);
  signal DCU_PLB_MSSize  : std_logic;

  signal net_gnd0  : std_logic;
  signal net_gnd3  : std_logic_vector(0 to 2);
  signal net_gnd64 : std_logic_vector(0 to 63);

  signal net_vcc0 : std_logic;
  signal net_vcc8 : std_logic_vector(0 to 7);

  signal DETERMINISTIC_MULT         : std_logic;
  signal DISABLE_OPERAND_FORWARDING : std_logic;
  signal MMU_ENABLE                 : std_logic;

  -- Resynchronisation signals for DCR interface
  signal DCRC405ACK_D     : std_logic;                  -- delayed 1 DCRCLK
  signal C405DCRWRITE_E   : std_logic;                  -- early 1 DCRCLK
  signal C405DCRREAD_E    : std_logic;                  -- early 1 DCRCLK
  signal DCRC405DBUSIN_D    : std_logic_vector(0 to 31);  -- delayed 1 DCRCLK
  signal C405DCRABUS_E    : std_logic_vector(0 to 9);  -- early 1 DCRCLK
  signal C405DCRDBUSOUT_E : std_logic_vector(0 to 31);  -- early 1 DCRCLK

  -- shared signal between two ppc405s
  signal C405JTGTDO_PPC_0 : std_logic;
  -- comparison of signals between the two ppc405s
  signal C405PLBICUREQUEST_PPC_0 : std_logic;
  signal C405PLBICUREQUEST_PPC_1 : std_logic;
  
begin

--------------------------------------------------------------------------------
-- Power assignments
  net_gnd0          <= '0';
  net_gnd3          <= "000";
  net_gnd64         <= "0000000000000000000000000000000000000000000000000000000000000000";
  net_vcc0          <= '1';
  net_vcc8          <= "11111111";
--------------------------------------------------------------------------------
-- Top-level port ICU assignments
  C405PLBICUABUS    <= ICU_PLB_ABus & "00";
  C405PLBICUBE      <= net_vcc8;
  C405PLBICURNW     <= net_vcc0;
  C405PLBICUBUSLOCK <= net_gnd0;
  C405PLBICUGUARDED <= net_gnd0;
  C405PLBICULOCKERR <= net_gnd0;
  C405PLBICUMSIZE   <= "01";
  C405PLBICUORDERED <= net_gnd0;
  C405PLBICURDBURST <= net_gnd0;
  C405PLBICUSIZE    <= "00" & ICU_PLB_SIZE;
  C405PLBICUTYPE    <= net_gnd3;
  C405PLBICUWRBURST <= net_gnd0;
  C405PLBICUWRDBUS  <= net_gnd64;

  ICU_PLB_MRdDBus <= PLBC405ICURDWDADDR(1 to 3);
  ICU_PLB_MSSize  <= PLBC405ICUSSIZE(1);

-- Top-level port DCU assignments
  C405PLBDCUBUSLOCK <= net_gnd0;
  C405PLBDCULOCKERR <= net_vcc0;
  C405PLBDCUMSIZE   <= "01";
  C405PLBDCUORDERED <= net_gnd0;
  C405PLBDCURDBURST <= net_gnd0;
  C405PLBDCUSIZE    <= "00" & DCU_PLB_SIZE2 & '0';
  C405PLBDCUTYPE    <= net_gnd3;
  C405PLBDCUWRBURST <= net_gnd0;

  DCU_PLB_MRdDBus <= PLBC405DCURDWDADDR(1 to 3);
  DCU_PLB_MSSize  <= PLBC405DCUSSIZE(1);

  DETERMINISTIC_MULT         <= '0' when C_DETERMINISTIC_MULT = 0         else '1';
  DISABLE_OPERAND_FORWARDING <= '0' when C_DISABLE_OPERAND_FORWARDING = 0 else '1';
  MMU_ENABLE                 <= '0' when C_MMU_ENABLE = 0                 else '1';

--------------------------------------------------------------------------------

-------------------------------------------------------------------------------
-- DCR pipeline registers for DCR interface timing. 
-------------------------------------------------------------------------------

  Full_DCR_Resync   : if (C_DCR_RESYNC = 2) generate begin
    FD_I_ACK       : FD port map (Q => DCRC405ACK_D, C => DCRCLK, D => DCRC405ACK);
    FD_I_READ      : FD port map (Q => C405DCRREAD, C => DCRCLK, D => C405DCRREAD_E);
    FD_I_WRITE     : FD port map (Q => C405DCRWRITE, C => DCRCLK, D => C405DCRWRITE_E);

    DCRDBUS_Resync  : for i in 0 to 31 generate begin
      FD_I_DBUSOUT : FD port map (Q => C405DCRDBUSOUT(i), C => DCRCLK, D => C405DCRDBUSOUT_E(i));
      FD_I_DBUSIN  : FD port map (Q => DCRC405DBUSIN_D(i), C => DCRCLK, D => DCRC405DBUSIN(i));
    end generate DCRDBUS_Resync;

    DCRABUS_Resync   : for i in 0 to 9 generate begin
      FD_I_ABUS    : FD port map (Q => C405DCRABUS(i), C => DCRCLK, D => C405DCRABUS_E(i));
    end generate DCRABUS_Resync;
  end generate Full_DCR_Resync;

  Ctrl_DCR_Resync : if (C_DCR_RESYNC = 1) generate begin
    FD_I_ACK     : FD port map (Q => DCRC405ACK_D, C => DCRCLK, D => DCRC405ACK);
    FD_I_READ    : FD port map (Q => C405DCRREAD, C => DCRCLK, D => C405DCRREAD_E);
    FD_I_WRITE   : FD port map (Q => C405DCRWRITE, C => DCRCLK, D => C405DCRWRITE_E);

    C405DCRABUS     <= C405DCRABUS_E;     -- not resynchronized
    C405DCRDBUSOUT  <= C405DCRDBUSOUT_E;  -- not resynchronized
    DCRC405DBUSIN_D <= DCRC405DBUSIN;       -- not resynchronized
  end generate Ctrl_DCR_Resync;

  No_DCR_Resync : if (C_DCR_RESYNC = 0) generate begin
    C405DCRREAD     <= C405DCRREAD_E;     -- not resynchronized
    C405DCRWRITE    <= C405DCRWRITE_E;    -- not resynchronized
    DCRC405ACK_D    <= DCRC405ACK;        -- not resynchronized
    C405DCRABUS     <= C405DCRABUS_E;     -- not resynchronized
    C405DCRDBUSOUT  <= C405DCRDBUSOUT_E;  -- not resynchronized
    DCRC405DBUSIN_D <= DCRC405DBUSIN;       -- not resynchronized
  end generate No_DCR_Resync;

  -- output assignments
  C405PLBICUREQUEST <= C405PLBICUREQUEST_PPC_0;
  -- flip-flop to store lockstep error signal
  process(PLBCLK, RSTC405RESETCHIP, RSTC405RESETCORE,
          RSTC405RESETSYS, C405PLBICUREQUEST_PPC_0,
          C405PLBICUREQUEST_PPC_1)
  begin
    if ( (RSTC405RESETCORE = '1') or
         (RSTC405RESETCORE = '1') or
         (RSTC405RESETCORE = '1') )
    then
      lockstep_error <= '0';
    elsif (PLBCLK = '1' and PLBCLK'event) then
      if (C405PLBICUREQUEST_PPC_0 /= C405PLBICUREQUEST_PPC_1)
      then
        lockstep_error <= '1';
      end if;
    end if;
  end process;
  
----------------------------------------------------------------------------
-- Instantiate PPC405 Processor Block Module
----------------------------------------------------------------------------