ppc405_top.vhd

PPC405 Lockstep System on ML310代码

-------------------------------------------------------------------------------
--$Id: ppc405_top.vhd,v 1.5.2.1 2004/08/05 00:49:27 larsg Exp $
------------------------------------------------------------------------------
-- PPC405 wrapper - Top Level Module
-------------------------------------------------------------------------------
--
--               THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
--               WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
--               IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--               A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--               THESE DESIGNS ARE XILINX CONFIDENTIAL MATERIAL
--               PROVIDED UNDER NDA.
--
--               Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
--               All rights reserved
--
------------------------------------------------------------------------------
-- Filename:       ppc405_top.vhd
-- Version:        v1.00a
-- Description:
--   This module is the top level file for the PLB Slave to OPB Master
--
-- Design Notes:
-------------------------------------------------------------------------------
-- Structure:
-------------------------------------------------------------------------------
-- Author:
-- History:
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_Gmm
-- Added high address parameters for OCM DCR address ranges
-- to aid addressgen tool. No functional change.
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Naming Conventions:
--      active low signals:                     "*_n"
--      clock signals:                          "clk", "clk_div#", "clk_#x"
--      reset signals:                          "rst", "rst_n"
--      generics/parameters:                    "C_*"
--      user defined types:                     "*_TYPE"
--      state machine next state:               "*_ns"
--      state machine current state:            "*_cs"
--      combinatorial signals:                  "*_cmb"
--      pipelined or register delay signals:    "*_d#"
--      counter signals:                        "*cnt*"
--      clock enable signals:                   "*_ce"
--      internal version of output port         "*_i"
--      device pins:                            "*_pin"
--      ports:                                  - Names begin with Uppercase
--      processes:                              "*_PROCESS"
--      component instantiations:               "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

library unisim;
use unisim.vcomponents.all;

-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------

entity ppc405_top is
  generic (
    C_ISOCM_DCR_BASEADDR         : std_logic_vector(0 to 9) := "0000010000";
    C_ISOCM_DCR_HIGHADDR         : std_logic_vector(0 to 9) := "0000010011";
    C_DSOCM_DCR_BASEADDR         : std_logic_vector(0 to 9) := "0000100000";
    C_DSOCM_DCR_HIGHADDR         : std_logic_vector(0 to 9) := "0000100011";
    C_DISABLE_OPERAND_FORWARDING : integer                  := 1;
    C_MMU_ENABLE                 : integer                  := 1;
    C_DETERMINISTIC_MULT         : integer                  := 0;
    C_DCR_RESYNC                 : integer                  := 0
    );

  port (
    -- Clock and Power Management Interface / CPU Control Interface
    C405CPMCORESLEEPREQ    : out std_logic;
    C405CPMMSRCE           : out std_logic;
    C405CPMMSREE           : out std_logic;
    C405CPMTIMERIRQ        : out std_logic;
    C405CPMTIMERRESETREQ   : out std_logic;
    C405XXXMACHINECHECK    : out std_logic;
    CPMC405CLOCK           : in  std_logic;
    CPMC405CORECLKINACTIVE : in  std_logic;
    CPMC405CPUCLKEN        : in  std_logic;
    CPMC405JTAGCLKEN       : in  std_logic;
    CPMC405TIMERCLKEN      : in  std_logic;
    CPMC405TIMERTICK       : in  std_logic;
    MCBCPUCLKEN            : in  std_logic;
    MCBTIMEREN             : in  std_logic;
    MCPPCRST               : in  std_logic;
    PLBCLK                 : in  std_logic;
    DCRCLK                 : in  std_logic;  -- clock for pipelining DCR interface
    
    -- Reset Interface
    C405RSTCHIPRESETREQ : out std_logic;
    C405RSTCORERESETREQ : out std_logic;
    C405RSTSYSRESETREQ  : out std_logic;
    RSTC405RESETCHIP    : in  std_logic;
    RSTC405RESETCORE    : in  std_logic;
    RSTC405RESETSYS     : in  std_logic;

    -- Instruction Cache Unit PLB Interface
    C405PLBICUABUS        : out std_logic_vector(0 to 31);  -- [0:29]
    C405PLBICUBE          : out std_logic_vector(0 to 7);   -- M_BE
    C405PLBICURNW         : out std_logic;                  -- M_RNW
    C405PLBICUABORT       : out std_logic;
    C405PLBICUBUSLOCK     : out std_logic;                  -- M_busLock
    C405PLBICUU0ATTR      : out std_logic;
    C405PLBICUGUARDED     : out std_logic;                  -- M_guarded
    C405PLBICULOCKERR     : out std_logic;                  -- M_lockErr
    C405PLBICUMSIZE       : out std_logic_vector(0 to 1);   -- M_MSize
    C405PLBICUORDERED     : out std_logic;                  -- M_ordered
    C405PLBICUPRIORITY    : out std_logic_vector(0 to 1);
    C405PLBICURDBURST     : out std_logic;                  -- M_rdBurst
    C405PLBICUREQUEST     : out std_logic;
    C405PLBICUSIZE        : out std_logic_vector(0 to 3);   -- C405PLBICUSIZE
    C405PLBICUTYPE        : out std_logic_vector(0 to 2);   -- M_type
    C405PLBICUWRBURST     : out std_logic;                  -- M_wrBurst
    C405PLBICUWRDBUS      : out std_logic_vector(0 to 63);  -- M_wrDBus
    C405PLBICUCACHEABLE   : out std_logic;
    PLBC405ICUADDRACK     : in  std_logic;
    PLBC405ICUBUSY        : in  std_logic;
    PLBC405ICUERR         : in  std_logic;
    PLBC405ICURDBTERM     : in  std_logic;                  -- PLB_MRdBTerm
    PLBC405ICURDDACK      : in  std_logic;
    PLBC405ICURDDBUS      : in  std_logic_vector(0 to 63);
    PLBC405ICURDWDADDR    : in  std_logic_vector(0 to 3);   -- [1:3]
    PLBC405ICUREARBITRATE : in  std_logic;                  -- PLB_MRearbitrate
    PLBC405ICUWRBTERM     : in  std_logic;                  -- PLB_MWrBTerm
    PLBC405ICUWRDACK      : in  std_logic;                  -- PLB_MWrDAck
    PLBC405ICUSSIZE       : in  std_logic_vector(0 to 1);   -- PLB_MSSize
    PLBC405ICUSERR        : in  std_logic;                  -- PLB_SMErr
    PLBC405ICUSBUSYS      : in  std_logic;                  -- PLB_SMBusy

    -- Data Cache Unit PLB Interface
    C405PLBDCUABUS        : out std_logic_vector(0 to 31);
    C405PLBDCUBE          : out std_logic_vector(0 to 7);
    C405PLBDCURNW         : out std_logic;
    C405PLBDCUABORT       : out std_logic;
    C405PLBDCUBUSLOCK     : out std_logic;                 -- M_busLock
    C405PLBDCUU0ATTR      : out std_logic;
    C405PLBDCUGUARDED     : out std_logic;
    C405PLBDCULOCKERR     : out std_logic;                 -- M_lockErr
    C405PLBDCUMSIZE       : out std_logic_vector(0 to 1);  -- M_MSize
    C405PLBDCUORDERED     : out std_logic;                 -- M_ordered
    C405PLBDCUPRIORITY    : out std_logic_vector(0 to 1);
    C405PLBDCURDBURST     : out std_logic;                 -- M_rdBurst
    C405PLBDCUREQUEST     : out std_logic;
    C405PLBDCUSIZE        : out std_logic_vector(0 to 3);  -- C405PLBDCUSIZE2
    C405PLBDCUTYPE        : out std_logic_vector(0 to 2);  -- M_type
    C405PLBDCUWRBURST     : out std_logic;                 -- M_wrBurst
    C405PLBDCUWRDBUS      : out std_logic_vector(0 to 63);
    C405PLBDCUCACHEABLE   : out std_logic;
    C405PLBDCUWRITETHRU   : out std_logic;
    PLBC405DCUADDRACK     : in  std_logic;
    PLBC405DCUBUSY        : in  std_logic;
    PLBC405DCUERR         : in  std_logic;
    PLBC405DCURDBTERM     : in  std_logic;                 -- PLB_MRdBTerm
    PLBC405DCURDDACK      : in  std_logic;
    PLBC405DCURDDBUS      : in  std_logic_vector(0 to 63);
    PLBC405DCURDWDADDR    : in  std_logic_vector(0 to 3);  -- [1:3]
    PLBC405DCUREARBITRATE : in  std_logic;                 -- PLB_MRearbitrate
    PLBC405DCUWRBTERM     : in  std_logic;                 -- PLB_MWrBTerm
    PLBC405DCUWRDACK      : in  std_logic;
    PLBC405DCUSSIZE       : in  std_logic_vector(0 to 1);  -- PLB_MSSize
    PLBC405DCUSERR        : in  std_logic;                 -- PLB_SMErr
    PLBC405DCUSBUSYS      : in  std_logic;                 -- PLB_SMBusy

    -- Data Side XpressRAM Interface
    BRAMDSOCMCLK       : in  std_logic;
    BRAMDSOCMRDDBUS    : in  std_logic_vector(0 to 31);
    DSARCVALUE         : in  std_logic_vector(0 to 7);
    DSCNTLVALUE        : in  std_logic_vector(0 to 7);
    DSOCMBRAMABUS      : out std_logic_vector(8 to 29);
    DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3);
    DSOCMBRAMEN        : out std_logic;
    DSOCMBRAMWRDBUS    : out std_logic_vector(0 to 31);
    DSOCMBUSY          : out std_logic;

    -- Instruction Side XpressRAM Interface
    BRAMISOCMCLK         : in  std_logic;
    BRAMISOCMRDDBUS      : in  std_logic_vector(0 to 63);
    ISARCVALUE           : in  std_logic_vector(0 to 7);
    ISCNTLVALUE          : in  std_logic_vector(0 to 7);
    ISOCMBRAMEN          : out std_logic;
    ISOCMBRAMEVENWRITEEN : out std_logic;
    ISOCMBRAMODDWRITEEN  : out std_logic;
    ISOCMBRAMRDABUS      : out std_logic_vector(8 to 28);
    ISOCMBRAMWRABUS      : out std_logic_vector(8 to 28);
    ISOCMBRAMWRDBUS      : out std_logic_vector(0 to 31);

    -- Device Control Register (DCR) Interface
    C405DCRABUS    : out std_logic_vector(0 to 9);
    C405DCRDBUSOUT : out std_logic_vector(0 to 31);
    C405DCRREAD    : out std_logic;
    C405DCRWRITE   : out std_logic;
    DCRC405ACK     : in  std_logic;
    DCRC405DBUSIN  : in  std_logic_vector(0 to 31);

    -- Interrupt Controller Interface
    EICC405CRITINPUTIRQ : in std_logic;
    EICC405EXTINPUTIRQ  : in std_logic;

    -- JTAG Interface
    C405JTGCAPTUREDR  : out std_logic;
    C405JTGEXTEST     : out std_logic;
    C405JTGPGMOUT     : out std_logic;
    C405JTGSHIFTDR    : out std_logic;
    C405JTGTDO        : out std_logic;
    -- lockstep changes
    C405JTGTDOEN_PPC_0: out std_logic;
    C405JTGTDOEN_PPC_1: out std_logic;
    C405JTGUPDATEDR   : out std_logic;
    MCBJTAGEN         : in  std_logic;
    JTGC405BNDSCANTDO : in  std_logic;
    JTGC405TCK        : in  std_logic;
    JTGC405TDI        : in  std_logic;
    JTGC405TMS        : in  std_logic;
    JTGC405TRSTNEG    : in  std_logic;

    -- Debug Interface
    C405DBGMSRWE            : out std_logic;
    C405DBGSTOPACK          : out std_logic;
    C405DBGWBCOMPLETE       : out std_logic;
    C405DBGWBFULL           : out std_logic;
    C405DBGWBIAR            : out std_logic_vector(0 to 29);
    DBGC405DEBUGHALT        : in  std_logic;
    DBGC405EXTBUSHOLDACK    : in  std_logic;
    DBGC405UNCONDDEBUGEVENT : in  std_logic;

    -- Trace Interface
    C405TRCCYCLE               : out std_logic;
    C405TRCEVENEXECUTIONSTATUS : out std_logic_vector(0 to 1);
    C405TRCODDEXECUTIONSTATUS  : out std_logic_vector(0 to 1);
    C405TRCTRACESTATUS         : out std_logic_vector(0 to 3);
    C405TRCTRIGGEREVENTOUT     : out std_logic;
    C405TRCTRIGGEREVENTTYPE    : out std_logic_vector(0 to 10);
    TRCC405TRACEDISABLE        : in  std_logic;
    TRCC405TRIGGEREVENTIN      : in  std_logic;

    -- lockstep mismatch
    lockstep_error             : out std_logic
    );
end ppc405_top;

architecture structure of ppc405_top is

  component PPC405
    port (
      -- Clock and Power Management Interface / CPU Control Interface
      C405CPMCORESLEEPREQ      : out std_logic;
      C405CPMMSRCE             : out std_logic;
      C405CPMMSREE             : out std_logic;
      C405CPMTIMERIRQ          : out std_logic;
      C405CPMTIMERRESETREQ     : out std_logic;
      C405XXXMACHINECHECK      : out std_logic;
      CPMC405CLOCK             : in  std_logic;
      CPMC405CORECLKINACTIVE   : in  std_logic;
      CPMC405CPUCLKEN          : in  std_logic;
      CPMC405JTAGCLKEN         : in  std_logic;
      CPMC405TIMERCLKEN        : in  std_logic;
      CPMC405TIMERTICK         : in  std_logic;
      MCBCPUCLKEN              : in  std_logic;
      MCBTIMEREN               : in  std_logic;
      MCPPCRST                 : in  std_logic;
      PLBCLK                   : in  std_logic;