emif.c

TI 无线传输芯片CC1100用 TMS320C5509 驱动的发送程序

#include <csl_emif.h>

/*SDRAM的EMIF设置*/
EMIF_Config Config_EMIF = {
  0x022F, //0x022f	//EGCR  : the MEMFREQ = 001,the clock for the memory is equal to  1/2CLOCKOUT（72M） frequence
  			//		  the WPE = 0 ,forbiden the writing posting when we debug the EMIF
  			//        the MEMCEN = 1,the memory clock is reflected on the CLKMEM pin
  			//        the NOHOLD = 1,HOLD requests are not recognized by the EMIF 
  0xFFFF,	//EMI_RST: any write to this register resets the EMIF state machine
  0x3FFF,	//CE0_1:  CE0 space control register 1
  			//        MTYPE = 011,Synchronous DRAM(SDRAM),16-bit data bus width
  0xFFFF,   //CE0_2:  CE0 space control register 2
  0x00FF,   //CE0_3:  CE0 space control register 3
  			//        TIMEOUT = 0xFF;
  0x3FFF,	//CE1_1:  CE1 space control register 1
  0xFFFF,	//CE1_2:  CE1 space control register 2
  0x00FF,	//CE1_3:  CE1 space control register 3
  
  0x1215,//0x1229, //0x1222,//0X1226	//0x1215,//CE2_1:  CE2 space control register 1  MTYPE=001,
  0x1229,//0x5229,	//CE2_2:  CE2 space control register 2
  0x00FF,	//CE2_3:  CE2 space control register 3
  
  0x1229,	//CE3_1:  CE3 space control register 1
  0x5219,	//CE3_2:  CE3 space control register 2
  0x00FF,	//CE3_3:  CE3 space control register 3
  
  0x2111,//0x4122,//0x2911,   //SDC1:   SDRAM control register 1
  		//    TRC =  ；从刷新命令REFR到REFR/MRS/ACTV命令间隔CLKMEM周期数（01000）
  			//        SDSIZE = 0;SDWID = 0  ；16位宽，64Mb（00）
  			//        RFEN = 1 ；刷新使能 （1）
  			//     TRCD = 2 ；从ACTV命令到READ/WRITE命令CLKMEM周期数3（0010）
  		//     TRP  = 2 ；从DCAB命令到REFR/ACTV/MRS命令CLKMEM周期数3（0010）
  0x0578,//0x1010,//0x0410,	//SDPER : SDRAM period register
  			//		  7ns(144M?) *4096
  0xffff,//0x07FF,    //SDINIT: SDRAM initialization register
  			//        any write to this register to init the all CE spaces,
  			//        do it after hardware reset or power up the C55x device
  0x0131,//0x0151,//0x0131	//SDC2:	  SDRAM control register 2
  			//        SDACC = 0;//SDRAM数据总线宽度为16位宽
  			//        TMRD = 01; //ACTV/DCAB/REFR延迟CLKMEM周期数 （00）
  			//        TRAS = 0101;//SDRAS信号有效时持续CLKMEM周期数（0101）
  			//        TACTV2ACTV = 0001;SDRAS到SDRAS有效延迟CLKMEM周期数（0001）					  			//        TACTV2ACTV = 0001;SDRAS到SDRAS有效延迟CLKMEM周期数（0001）							
  };


void initEMIF(void)
{
  EMIF_config(&Config_EMIF);
  EMIF_FSET(EGCR,MEMCEN,0x0001);
}