mcbsp.c

TI 无线传输芯片CC1100用 TMS320C5509 驱动的发送程序

# include"csl_mcbsp.h"
MCBSP_Handle hMcbsp;

MCBSP_Config ConfigMcbsp= {
 0x3800,// 0x2000,   /* SPCR1*/
	        /* DLB=0b             digital loopback mode is disabled */
	        /* RJUST=01b          receive : right justify the data and sign-extend the data into the MSBs */
		    /* CLKSTP=11b         clock stop mode is enabled,10b(without clock delay);11b (with half_cycle clock delay)  */
		    /* Reserved=000b */
		    /* DXENA=0b           DX delay off */
		    /* ABIS=0b */
		    /* RINTM=00b          mcbsp send a receive interrupt request to CPU */
		    /* RSYNCERR=0b        no receive frame-sync error */
		    /* RFULL=0b           no receive-full condition */
			/* RRDY=0b            receiver not ready */
			/* RRST=0b            reset the receiver */
  0x0100,   /* SPCR2 */ 
            /* Reserved=000000b */
			/* FREE=0b            the mcbsp reansmit and receive clocks are affected as determined by the SOFT bit */
            /* SOFT=1b            when an emulation suspend event occurs, tramsmit clock stops after completion of the current serial word transfer */
			/* FRST=0b            reset frame-sync logic */
	        /* GRST=0b            reset sampl rate genarator */
			/* XINTM=00b          mcbsp send a tramsmit interrupt request to CPU */
			/* XSYNCERR=0b        no transmit frame-sync error */
			/* XEMPTY=0b          transmitter-empty condition */
			/* XRDY=0b            transmitter nor ready */
			/* XRST=0b            reset the transmitter */
  0x0000,   /* RCR1 */
            /* Reserved=0b */
			/* RFRLEN1=0000000b   one word per receive frame */
			/* RWDLEN1=000b       8 bit per word */
			/* Reserved=00000b */
  0x0005,   /* RCR2 */
            /* RPHASE=0b          receive : single-phase frame */
			/* RFRLEN2=0000000b*/
			/* RWDLEN2=000b*/
			/* RCOMPAND=00b       no companding, MSBs recevied first */
			/* RFIG=1b            unexpected FSR pulse is ignored */
			/* RDATDLY=01b         receive data 1-bit delay*/
  0x0000,   /* XCR1 */
            /* Reserved=0b */
			/* XFRLEN1=0000000b   one word per receive frame */
			/* XWDLEN1=000b       8 bit per word */
			/* Reserved=00000b */
  0x0005,   /* XCR2 */
            /* XPHASE=0b          transmit : single-phase frame */
			/* XFRLEN2=0000000b*/
			/* XWDLEN2=000b*/
			/* XCOMPAND=00b       no companding, MSBs transmitted first */
			/* XFIG=1b            unexpected FSR pulse is ignored */
			/* XDATDLY=01b         transmit data 1-bit delay*/
  0x008F,   /* SRGR1 */
            /* FWID=0b            frame-sync pulse width is 1 CLKG cycle*/
			/* CLKGDV=10001111//00001011b   CLKG=144MHz/(CLKGDV+1)=1MHz*/
  0x200F,   /* SRGR2 */
            /* GSYNC=0b           no clock synchronization */
			/* CLKSP=0b */
			/* CLKSM=1b           SCLKME=0,CLKSM=1, the input clock for the sample rate generator is derived from the CPU */
			/* FSGM=0b            frame-sync pulses generated every time data is transferred from DXR1 to XSR1 */
			/* FPER=000000000000b the period between frame-sync pulse is (FPER+1) CLKG cycles ,ignored*/
  0x0000,   /* MCR1 */
  0x0000,   /* MCR2 */
  0x0F09,   /* PCR */
            /* Reserved=0b */
			/* IDLEEN=0b          the McBSP remain active when the PERIPH domain is idled */
			/* XIOEN=0b           the CLKX,FSX,DX are serial port pins */
			/* RIOEN=0b           the CLKR,FSR,DR are serial port pins */
			/* FSXM=1b            transmit frame synchronization is supplied by the McBSP */
			/* FSRM=1b            receive frame synchronization is supplied by the McBSP*/
			/* CLKXM=1b           CLKX is driven by the sample rate generator */
			/* CLKRM=1b           CLKr is driven by the sample rate genetator */
			/* SCLKME=0b */
			/* CLKSSTAT=0b */
			/* DXSTAT=0b */
			/* DRSTAT=0b */
			/* FSXP=1b            transmit frame-sync pulse are active low */
			/* FSRP=0b            receive frame-sync pulse are active high */
			/* CLKXP=0b           transmit data is driven on the rising edge of CLKX */
			/* CLKRP=1b           receive data is driven on the rising edge of CLKR*/
  0x0000,   /* RCERA */
  0x0000,   /* RCERB */
  0x0000,   /* RCERC */
  0x0000,   /* RCERD */
  0x0000,   /* RCERE */
  0x0000,   /* RCERF */
  0x0000,   /* RCERG */
  0x0000,   /* RCERH */
  0x0000,   /* XCERA */
  0x0000,   /* XCERB */
  0x0000,   /* XCERC */
  0x0000,   /* XCERD */
  0x0000,   /* XCERE */
  0x0000,   /* XCERF */
  0x0000,   /* XCERG */
  0x0000    /* XCERH */
};

void mcbsp_init()
{
  hMcbsp=MCBSP_open(MCBSP_PORT0,MCBSP_OPEN_RESET);
  MCBSP_config(hMcbsp,&ConfigMcbsp);
 // MCBSP_SPCR20_FSET( MCBSP_SPCR2_GRST,0);
}