m32r.c

来自「GCC编译器源代码」· C语言 代码 · 共 1,836 行 · 第 1/4 页

{
  if (GET_CODE (op) == SUBREG)
    op = SUBREG_REG (op);
  if (GET_CODE (op) != MEM)
    return 0;
  op = XEXP (op, 0);
  return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
	  || GET_CODE (op) == LABEL_REF);
}

/* Return 1 if OP is a reference to an object in .sdata/.sbss.  */

int
small_data_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (! TARGET_SDATA_USE)
    return 0;

  if (GET_CODE (op) == SYMBOL_REF)
    return SDATA_NAME_P (XSTR (op, 0));

  if (GET_CODE (op) == CONST
      && GET_CODE (XEXP (op, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
      && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
    return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));

  return 0;
}

/* Return 1 if OP is a symbol that can use 24 bit addressing.  */

int
addr24_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == LABEL_REF)
    return TARGET_ADDR24;

  if (GET_CODE (op) == SYMBOL_REF)
    return (SMALL_NAME_P (XSTR (op, 0))
	    || (TARGET_ADDR24
		&& (CONSTANT_POOL_ADDRESS_P (op)
		    || LIT_NAME_P (XSTR (op, 0)))));

  if (GET_CODE (op) == CONST
      && GET_CODE (XEXP (op, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
      && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
    {
      rtx sym = XEXP (XEXP (op, 0), 0);
      return (SMALL_NAME_P (XSTR (sym, 0))
	      || (TARGET_ADDR24
		  && (CONSTANT_POOL_ADDRESS_P (op)
		      || LIT_NAME_P (XSTR (op, 0)))));
    }

  return 0;
}

/* Return 1 if OP is a symbol that needs 32 bit addressing.  */

int
addr32_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == LABEL_REF)
    return TARGET_ADDR32;

  if (GET_CODE (op) == SYMBOL_REF)
    return (! addr24_operand (op)
	    && ! small_data_operand (op));

  if (GET_CODE (op) == CONST
      && GET_CODE (XEXP (op, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
    {
      return (! addr24_operand (op)
	      && ! small_data_operand (op));
    }

  return 0;
}

/* Return 1 if OP is a function that can be called with the `bl' insn.  */

int
call26_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == SYMBOL_REF)
    return ! LARGE_NAME_P (XSTR (op, 0));

  return TARGET_CALL26;
}

/* Return 1 if OP is a function that must be called with 32 bit addressing.  */

int
call32_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  return ! call26_operand (op, mode);
}

/* Returns 1 if OP is an acceptable operand for seth/add3.  */

int
seth_add3_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == SYMBOL_REF
      || GET_CODE (op) == LABEL_REF)
    return 1;

  if (GET_CODE (op) == CONST
      && GET_CODE (XEXP (op, 0)) == PLUS
      && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
      && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
      && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
    return 1;

  return 0;
}

/* Return true if OP is a signed 8 bit immediate value.  */

int
int8_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return INT8_P (INTVAL (op));
}

/* Return true if OP is a signed 16 bit immediate value.  */

int
int16_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return INT16_P (INTVAL (op));
}

/* Return true if OP is a signed 16 bit immediate value
   useful in comparisons.  */

int
cmp_int16_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return CMP_INT16_P (INTVAL (op));
}

/* Return true if OP is an unsigned 16 bit immediate value.  */

int
uint16_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return UINT16_P (INTVAL (op));
}

/* Return true if OP is an unsigned 24 bit immediate value.  */

int
uint24_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return UINT24_P (INTVAL (op));
}

/* Return true if OP is a register or signed 8 bit value.  */

int
reg_or_int8_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
    return register_operand (op, mode);
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return INT8_P (INTVAL (op));
}

/* Return true if OP is a register or signed 8 bit value.  */

int
reg_or_int16_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
    return register_operand (op, mode);
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return INT16_P (INTVAL (op));
}

/* Return true if OP is a register or signed 8 bit value.  */

int
reg_or_uint16_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
    return register_operand (op, mode);
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return UINT16_P (INTVAL (op));
}

/* Return true if OP is a register or signed 16 bit value for compares.  */

int
reg_or_cmp_int16_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
    return register_operand (op, mode);
  if (GET_CODE (op) != CONST_INT)
    return 0;
  return CMP_INT16_P (INTVAL (op));
}

/* Return true if OP is a const_int requiring two instructions to load.  */

int
two_insn_const_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  if (GET_CODE (op) != CONST_INT)
    return 0;
  if (INT16_P (INTVAL (op))
      || UINT24_P (INTVAL (op))
      || UPPER16_P (INTVAL (op)))
    return 0;
  return 1;
}

/* Return true if OP is an acceptable argument for a single word
   move source.  */

int
move_src_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  switch (GET_CODE (op))
    {
    case SYMBOL_REF :
    case CONST :
      return addr24_operand (op, mode);
    case CONST_INT :
      /* ??? We allow more cse opportunities if we only allow constants
	 loadable with one insn, and split the rest into two.  The instances
	 where this would help should be rare and the current way is
	 simpler.  */
      return INT32_P (INTVAL (op));
    case LABEL_REF :
      return TARGET_ADDR24;
    case CONST_DOUBLE :
      if (mode == SFmode)
	return 1;
      else if (mode == SImode)
	{
	  /* Large unsigned constants are represented as const_double's.  */
	  unsigned HOST_WIDE_INT low, high;

	  low = CONST_DOUBLE_LOW (op);
	  high = CONST_DOUBLE_HIGH (op);
	  return high == 0 && low <= 0xffffffff;
	}
      else
	return 0;
    case REG :
      return register_operand (op, mode);
    case SUBREG :
      /* (subreg (mem ...) ...) can occur here if the inner part was once a
	 pseudo-reg and is now a stack slot.  */
      if (GET_CODE (SUBREG_REG (op)) == MEM)
	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
      else
	return register_operand (op, mode);
    case MEM :
      return address_operand (XEXP (op, 0), mode);
    default :
      return 0;
    }
}

/* Return true if OP is an acceptable argument for a double word
   move source.  */

int
move_double_src_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  switch (GET_CODE (op))
    {
    case CONST_INT :
    case CONST_DOUBLE :
      if (mode == DFmode)
	return easy_df_const (op);
      else
	return easy_di_const (op);
    case REG :
      return register_operand (op, mode);
    case SUBREG :
      /* (subreg (mem ...) ...) can occur here if the inner part was once a
	 pseudo-reg and is now a stack slot.  */
      if (GET_CODE (SUBREG_REG (op)) == MEM)
	return move_double_src_operand (SUBREG_REG (op), mode);
      else
	return register_operand (op, mode);
    case MEM :
      /* Disallow auto inc/dec for now.  */
      if (GET_CODE (XEXP (op, 0)) == PRE_DEC
	  || GET_CODE (XEXP (op, 0)) == PRE_INC)
	return 0;
      return address_operand (XEXP (op, 0), mode);
    default :
      return 0;
    }
}

/* Return true if OP is an acceptable argument for a move destination.  */

int
move_dest_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  switch (GET_CODE (op))
    {
    case REG :
      return register_operand (op, mode);
    case SUBREG :
      /* (subreg (mem ...) ...) can occur here if the inner part was once a
	 pseudo-reg and is now a stack slot.  */
      if (GET_CODE (SUBREG_REG (op)) == MEM)
	return address_operand (XEXP (SUBREG_REG (op), 0), mode);
      else
	return register_operand (op, mode);
    case MEM :
      return address_operand (XEXP (op, 0), mode);
    default :
      return 0;
    }
}

/* Return 1 if OP is a DImode const we want to handle inline.
   This must match the code in the movdi pattern.
   It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER.  */

int
easy_di_const (op)
     rtx op;
{
  rtx high_rtx, low_rtx;
  HOST_WIDE_INT high, low;

  split_double (op, &high_rtx, &low_rtx);
  high = INTVAL (high_rtx);
  low = INTVAL (low_rtx);
  /* Pick constants loadable with 2 16 bit `ldi' insns.  */
  if (high >= -128 && high <= 127
      && low >= -128 && low <= 127)
    return 1;
  return 0;
}

/* Return 1 if OP is a DFmode const we want to handle inline.
   This must match the code in the movdf pattern.
   It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER.  */

int
easy_df_const (op)
     rtx op;
{
  REAL_VALUE_TYPE r;
  long l[2];

  REAL_VALUE_FROM_CONST_DOUBLE (r, op);
  REAL_VALUE_TO_TARGET_DOUBLE (r, l);
  if (l[0] == 0 && l[1] == 0)
    return 1;
  if ((l[0] & 0xffff) == 0 && l[1] == 0)
    return 1;
  return 0;
}

/* Return 1 if OP is an EQ or NE comparison operator.  */

int
eqne_comparison_operator (op, mode)
    rtx op;
    enum machine_mode mode;
{
  enum rtx_code code = GET_CODE (op);

  if (GET_RTX_CLASS (code) != '<')
    return 0;
  return (code == EQ || code == NE);
}

/* Return 1 if OP is a signed comparison operator.  */

int
signed_comparison_operator (op, mode)
    rtx op;
    enum machine_mode mode;
{
  enum rtx_code code = GET_CODE (op);

  if (GET_RTX_CLASS (code) != '<')
    return 0;
  return (code == EQ || code == NE
	  || code == LT || code == LE || code == GT || code == GE);
}

/* Return 1 if OP is (mem (reg ...)).
   This is used in insn length calcs.  */

int
memreg_operand (op, mode)
     rtx op;
     enum machine_mode mode;
{
  return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;