sparc.h
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1,699 行
#define MASK_EPILOGUE 2#define TARGET_EPILOGUE (target_flags & MASK_EPILOGUE)/* Nonzero if we should assume that double pointers might be unaligned. This can happen when linking gcc compiled code with other compilers, because the ABI only guarantees 4 byte alignment. */#define MASK_UNALIGNED_DOUBLES 4#define TARGET_UNALIGNED_DOUBLES (target_flags & MASK_UNALIGNED_DOUBLES)/* Nonzero means that we should generate code for a v8 sparc. */#define MASK_V8 0x8#define TARGET_V8 (target_flags & MASK_V8)/* Nonzero means that we should generate code for a sparclite. This enables the sparclite specific instructions, but does not affect whether FPU instructions are emitted. */#define MASK_SPARCLITE 0x10#define TARGET_SPARCLITE (target_flags & MASK_SPARCLITE)/* Nonzero if we're compiling for the sparclet. */#define MASK_SPARCLET 0x20#define TARGET_SPARCLET (target_flags & MASK_SPARCLET)/* Nonzero if we're compiling for v9 sparc. Note that v9's can run in 32 bit mode so this doesn't necessarily mean the word size is 64. */#define MASK_V9 0x40#define TARGET_V9 (target_flags & MASK_V9)/* Non-zero to generate code that uses the instructions deprecated in the v9 architecture. This option only applies to v9 systems. *//* ??? This isn't user selectable yet. It's used to enable such insns on 32 bit v9 systems and for the moment they're permanently disabled on 64 bit v9 systems. */#define MASK_DEPRECATED_V8_INSNS 0x80#define TARGET_DEPRECATED_V8_INSNS (target_flags & MASK_DEPRECATED_V8_INSNS)/* Mask of all CPU selection flags. */#define MASK_ISA \(MASK_V8 + MASK_SPARCLITE + MASK_SPARCLET + MASK_V9 + MASK_DEPRECATED_V8_INSNS)/* Non-zero means don't pass `-assert pure-text' to the linker. */#define MASK_IMPURE_TEXT 0x100#define TARGET_IMPURE_TEXT (target_flags & MASK_IMPURE_TEXT)/* Nonzero means that we should generate code using a flat register window model, i.e. no save/restore instructions are generated, which is compatible with normal sparc code. The frame pointer is %i7 instead of %fp. */#define MASK_FLAT 0x200#define TARGET_FLAT (target_flags & MASK_FLAT)/* Nonzero means use the registers that the Sparc ABI reserves for application software. This must be the default to coincide with the setting in FIXED_REGISTERS. */#define MASK_APP_REGS 0x400#define TARGET_APP_REGS (target_flags & MASK_APP_REGS)/* Option to select how quad word floating point is implemented. When TARGET_HARD_QUAD is true, we use the hardware quad instructions. Otherwise, we use the SPARC ABI quad library functions. */#define MASK_HARD_QUAD 0x800#define TARGET_HARD_QUAD (target_flags & MASK_HARD_QUAD)/* Non-zero on little-endian machines. *//* ??? Little endian support currently only exists for sparclet-aout and sparc64-elf configurations. May eventually want to expand the support to all targets, but for now it's kept local to only those two. */#define MASK_LITTLE_ENDIAN 0x1000#define TARGET_LITTLE_ENDIAN (target_flags & MASK_LITTLE_ENDIAN)/* 0x2000, 0x4000 are unused *//* Nonzero if pointers are 64 bits. This is not a user selectable option, though it may be one day - so it is used to determine pointer size instead of an architecture flag. */#define MASK_PTR64 0x8000#define TARGET_PTR64 (target_flags & MASK_PTR64)/* Nonzero if generating code to run in a 64 bit environment. This is intended to only be used by TARGET_ARCH{32,64} as they are the mechanism used to control compile time or run time selection. */#define MASK_64BIT 0x10000#define TARGET_64BIT (target_flags & MASK_64BIT)/* 0x20000,0x40000 unused *//* Non-zero means use a stack bias of 2047. Stack offsets are obtained by adding 2047 to %sp. This option is for v9 only and is the default. */#define MASK_STACK_BIAS 0x80000#define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)/* Non-zero means %g0 is a normal register. We still clobber it as necessary, but we can't rely on it always having a zero value. We don't bother to support this in true 64 bit mode. */#define MASK_LIVE_G0 0x100000#define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)/* Non-zero means the cpu has broken `save' and `restore' insns, only the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0). We assume the environment will properly handle or otherwise avoid trouble associated with an interrupt occurring after the `save' or trap occurring during it. */#define MASK_BROKEN_SAVERESTORE 0x200000#define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)/* Non-zero means -m{,no-}fpu was passed on the command line. */#define MASK_FPU_SET 0x400000#define TARGET_FPU_SET (target_flags & MASK_FPU_SET)/* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, each pair being { "NAME", VALUE } where VALUE is the bits to set or minus the bits to clear. An empty string NAME is used to identify the default VALUE. */#define TARGET_SWITCHES \ { {"fpu", MASK_FPU | MASK_FPU_SET}, \ {"no-fpu", -MASK_FPU}, \ {"no-fpu", MASK_FPU_SET}, \ {"hard-float", MASK_FPU | MASK_FPU_SET}, \ {"soft-float", -MASK_FPU}, \ {"soft-float", MASK_FPU_SET}, \ {"epilogue", MASK_EPILOGUE}, \ {"no-epilogue", -MASK_EPILOGUE}, \ {"unaligned-doubles", MASK_UNALIGNED_DOUBLES}, \ {"no-unaligned-doubles", -MASK_UNALIGNED_DOUBLES}, \ {"impure-text", MASK_IMPURE_TEXT}, \ {"no-impure-text", -MASK_IMPURE_TEXT}, \ {"flat", MASK_FLAT}, \ {"no-flat", -MASK_FLAT}, \ {"app-regs", MASK_APP_REGS}, \ {"no-app-regs", -MASK_APP_REGS}, \ {"hard-quad-float", MASK_HARD_QUAD}, \ {"soft-quad-float", -MASK_HARD_QUAD}, \ /* ??? These are deprecated, coerced to -mcpu=. Delete in 2.9. */ \ {"cypress", 0}, \ {"sparclite", 0}, \ {"f930", 0}, \ {"f934", 0}, \ {"v8", 0}, \ {"supersparc", 0}, \ /* End of deprecated options. */ \ /* -mptrNN exists for *experimental* purposes. */ \/* {"ptr64", MASK_PTR64}, */ \/* {"ptr32", -MASK_PTR64}, */ \ {"32", -MASK_64BIT}, \ {"64", MASK_64BIT}, \ {"stack-bias", MASK_STACK_BIAS}, \ {"no-stack-bias", -MASK_STACK_BIAS}, \ SUBTARGET_SWITCHES \ { "", TARGET_DEFAULT}}/* MASK_APP_REGS must always be the default because that's what FIXED_REGISTERS is set to and -ffixed- is processed before CONDITIONAL_REGISTER_USAGE is called (where we process -mno-app-regs). */#define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE + MASK_FPU)/* This is meant to be redefined in target specific files. */#define SUBTARGET_SWITCHES/* Processor type. These must match the values for the cpu attribute in sparc.md. */enum processor_type { PROCESSOR_V7, PROCESSOR_CYPRESS, PROCESSOR_V8, PROCESSOR_SUPERSPARC, PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, PROCESSOR_SPARCLET, PROCESSOR_TSC701, PROCESSOR_V8PLUS, PROCESSOR_V9, PROCESSOR_ULTRASPARC};/* This is set from -m{cpu,tune}=xxx. */extern enum processor_type sparc_cpu;/* Recast the cpu class to be the cpu attribute. Every file includes us, but not every file includes insn-attr.h. */#define sparc_cpu_attr ((enum attr_cpu) sparc_cpu)/* This macro is similar to `TARGET_SWITCHES' but defines names of command options that have values. Its definition is an initializer with a subgrouping for each command option. Each subgrouping contains a string constant, that defines the fixed part of the option name, and the address of a variable. The variable, type `char *', is set to the variable part of the given option if the fixed part matches. The actual option name is made by appending `-m' to the specified name. Here is an example which defines `-mshort-data-NUMBER'. If the given option is `-mshort-data-512', the variable `m88k_short_data' will be set to the string `"512"'. extern char *m88k_short_data; #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */#define TARGET_OPTIONS \{ \ { "cpu=", &sparc_select[1].string }, \ { "tune=", &sparc_select[2].string }, \ { "cmodel=", &sparc_cmodel_string }, \ { "align-loops=", &sparc_align_loops_string }, \ { "align-jumps=", &sparc_align_jumps_string }, \ { "align-functions=", &sparc_align_funcs_string }, \ SUBTARGET_OPTIONS \}/* This is meant to be redefined in target specific files. */#define SUBTARGET_OPTIONS/* sparc_select[0] is reserved for the default cpu. */struct sparc_cpu_select{ char *string; char *name; int set_tune_p; int set_arch_p;};extern struct sparc_cpu_select sparc_select[];/* Variables to record values the user passes. */extern char *sparc_align_loops_string;extern char *sparc_align_jumps_string;extern char *sparc_align_funcs_string;/* Parsed values as a power of two. */extern int sparc_align_loops;extern int sparc_align_jumps;extern int sparc_align_funcs;#define DEFAULT_SPARC_ALIGN_FUNCS \(sparc_cpu == PROCESSOR_ULTRASPARC ? 5 : 2)/* target machine storage layout *//* Define for cross-compilation to a sparc target with no TFmode from a host with a different float format (e.g. VAX). */#define REAL_ARITHMETIC/* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */#define BITS_BIG_ENDIAN 1/* Define this if most significant byte of a word is the lowest numbered. */#define BYTES_BIG_ENDIAN 1/* Define this if most significant word of a multiword number is the lowest numbered. */#define WORDS_BIG_ENDIAN 1/* Define this to set the endianness to use in libgcc2.c, which can not depend on target_flags. */#if defined (__LITTLE_ENDIAN__)#define LIBGCC2_WORDS_BIG_ENDIAN 0#else#define LIBGCC2_WORDS_BIG_ENDIAN 1#endif/* number of bits in an addressable storage unit */#define BITS_PER_UNIT 8/* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */#define BITS_PER_WORD (TARGET_ARCH64 ? 64 : 32)#define MAX_BITS_PER_WORD 64/* Width of a word, in units (bytes). */#define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4)#define MIN_UNITS_PER_WORD 4/* Now define the sizes of the C data types. */#define SHORT_TYPE_SIZE 16#define INT_TYPE_SIZE 32#define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32)#define LONG_LONG_TYPE_SIZE 64#define FLOAT_TYPE_SIZE 32#define DOUBLE_TYPE_SIZE 64#if defined (SPARC_BI_ARCH)#define MAX_LONG_TYPE_SIZE 64#endif#if 0/* ??? This does not work in SunOS 4.x, so it is not enabled here. Instead, it is enabled in sol2.h, because it does work under Solaris. *//* Define for support of TFmode long double and REAL_ARITHMETIC. Sparc ABI says that long double is 4 words. */#define LONG_DOUBLE_TYPE_SIZE 128#endif/* Width in bits of a pointer. See also the macro `Pmode' defined below. */#define POINTER_SIZE (TARGET_PTR64 ? 64 : 32)/* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and which has the specified mode and signedness is to be stored in a register. This macro is only called when TYPE is a scalar type. */#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \if (TARGET_ARCH64 \ && GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \{ \ (MODE) = DImode; \}/* Define this macro if the promotion described by PROMOTE_MODE should also be done for outgoing function arguments. *//* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test for this value. */#define PROMOTE_FUNCTION_ARGS/* Define this macro if the promotion described by PROMOTE_MODE should also be done for the return value of functions. If this macro is defined, FUNCTION_VALUE must perform the same promotions done by PROMOTE_MODE. *//* This is only needed for TARGET_ARCH64, but since PROMOTE_MODE is a no-op for TARGET_ARCH32 this is ok. Otherwise we'd need to add a runtime test for this value. */#define PROMOTE_FUNCTION_RETURN/* Allocation boundary (in *bits*) for storing arguments in argument list. */#define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32)/* Boundary (in *bits*) on which stack pointer should be aligned. */#define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64)/* ALIGN FRAMES on double word boundaries */
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