alpha.h

GCC编译器源代码

   CUM is as above.

   MODE and TYPE are the mode and type of the current parameter.

   PRETEND_SIZE is a variable that should be set to the amount of stack
   that must be pushed by the prolog to pretend that our caller pushed
   it.

   Normally, this macro will push all remaining incoming registers on the
   stack and set PRETEND_SIZE to the length of the registers pushed. 

   On the Alpha, we allocate space for all 12 arg registers, but only
   push those that are remaining.

   However, if NO registers need to be saved, don't allocate any space.
   This is not only because we won't need the space, but because AP includes
   the current_pretend_args_size and we don't want to mess up any
   ap-relative addresses already made.

   If we are not to use the floating-point registers, save the integer
   registers where we would put the floating-point registers.  This is
   not the most efficient way to implement varargs with just one register
   class, but it isn't worth doing anything more efficient in this rare
   case.  */
   

#define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL)	\
{ if ((CUM) < 6)							\
    {									\
      if (! (NO_RTL))							\
	{								\
	  move_block_from_reg						\
	    (16 + CUM,							\
	     gen_rtx (MEM, BLKmode,					\
		      plus_constant (virtual_incoming_args_rtx,		\
				     ((CUM) + 6)* UNITS_PER_WORD)),	\
	     6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD);			\
	  move_block_from_reg						\
	    (16 + (TARGET_FPREGS ? 32 : 0) + CUM,			\
	     gen_rtx (MEM, BLKmode,					\
		      plus_constant (virtual_incoming_args_rtx,		\
				     (CUM) * UNITS_PER_WORD)),		\
	     6 - (CUM), (6 - (CUM)) * UNITS_PER_WORD);			\
	 }								\
      PRETEND_SIZE = 12 * UNITS_PER_WORD;				\
    }									\
}

/* Try to output insns to set TARGET equal to the constant C if it can be
   done in less than N insns.  Do all computations in MODE.  Returns the place
   where the output has been placed if it can be done and the insns have been
   emitted.  If it would take more than N insns, zero is returned and no
   insns and emitted.  */
extern struct rtx_def *alpha_emit_set_const ();
extern struct rtx_def *alpha_emit_set_long_const ();
extern struct rtx_def *alpha_emit_conditional_move ();

/* Generate necessary RTL for __builtin_saveregs().
   ARGLIST is the argument list; see expr.c.  */
extern struct rtx_def *alpha_builtin_saveregs ();
#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) alpha_builtin_saveregs (ARGLIST)

/* Define the information needed to generate branch and scc insns.  This is
   stored from the compare operation.  Note that we can't use "rtx" here
   since it hasn't been defined!  */

extern struct rtx_def *alpha_compare_op0, *alpha_compare_op1;
extern int alpha_compare_fp_p;

/* Make (or fake) .linkage entry for function call.

   IS_LOCAL is 0 if name is used in call, 1 if name is used in definition.  */
extern void alpha_need_linkage ();

/* This macro produces the initial definition of a function name.  On the
   Alpha, we need to save the function name for the prologue and epilogue.  */

extern char *alpha_function_name;

#define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL)	\
{							\
   alpha_function_name = NAME;				\
}
   
/* This macro generates the assembly code for function entry.
   FILE is a stdio stream to output the code to.
   SIZE is an int: how many units of temporary storage to allocate.
   Refer to the array `regs_ever_live' to determine which registers
   to save; `regs_ever_live[I]' is nonzero if register number I
   is ever used in the function.  This macro is responsible for
   knowing which registers should not be saved even if used.  */

#define FUNCTION_PROLOGUE(FILE, SIZE)  output_prolog (FILE, SIZE)

/* Output assembler code to FILE to increment profiler label # LABELNO
   for profiling a function entry.  Under OSF/1, profiling is enabled
   by simply passing -pg to the assembler and linker.  */

#define FUNCTION_PROFILER(FILE, LABELNO)

/* Output assembler code to FILE to initialize this source file's
   basic block profiling info, if that has not already been done.
   This assumes that __bb_init_func doesn't garble a1-a5. */

#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)			\
    do {							\
	ASM_OUTPUT_REG_PUSH (FILE, 16);				\
	fputs ("\tlda $16,$PBX32\n", (FILE));			\
	fputs ("\tldq $26,0($16)\n", (FILE));			\
	fputs ("\tbne $26,1f\n", (FILE));			\
	fputs ("\tlda $27,__bb_init_func\n", (FILE));		\
	fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE));	\
	fputs ("\tldgp $29,0($26)\n", (FILE));			\
	fputs ("1:\n", (FILE));					\
	ASM_OUTPUT_REG_POP (FILE, 16);				\
    } while (0);

/* Output assembler code to FILE to increment the entry-count for
   the BLOCKNO'th basic block in this source file.  */

#define BLOCK_PROFILER(FILE, BLOCKNO)				\
    do {							\
	int blockn = (BLOCKNO);					\
	fputs ("\tsubq $30,16,$30\n", (FILE));			\
	fputs ("\tstq $26,0($30)\n", (FILE));			\
	fputs ("\tstq $27,8($30)\n", (FILE));			\
	fputs ("\tlda $26,$PBX34\n", (FILE));			\
	fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn);	\
	fputs ("\taddq $27,1,$27\n", (FILE));			\
	fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn);	\
	fputs ("\tldq $26,0($30)\n", (FILE));			\
	fputs ("\tldq $27,8($30)\n", (FILE));			\
	fputs ("\taddq $30,16,$30\n", (FILE));			\
    } while (0)


/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
   the stack pointer does not matter.  The value is tested only in
   functions that have frame pointers.
   No definition is equivalent to always zero.  */

#define EXIT_IGNORE_STACK 1

/* This macro generates the assembly code for function exit,
   on machines that need it.  If FUNCTION_EPILOGUE is not defined
   then individual return instructions are generated for each
   return statement.  Args are same as for FUNCTION_PROLOGUE.

   The function epilogue should not depend on the current stack pointer!
   It should use the frame pointer only.  This is mandatory because
   of alloca; we also take advantage of it to omit stack adjustments
   before returning.  */

#define FUNCTION_EPILOGUE(FILE, SIZE)	output_epilog (FILE, SIZE)


/* Output assembler code for a block containing the constant parts
   of a trampoline, leaving space for the variable parts.

   The trampoline should set the static chain pointer to value placed
   into the trampoline and should branch to the specified routine.  
   Note that $27 has been set to the address of the trampoline, so we can
   use it for addressability of the two data items.  Trampolines are always
   aligned to FUNCTION_BOUNDARY, which is 64 bits.  */

#define TRAMPOLINE_TEMPLATE(FILE)		\
{						\
  fprintf (FILE, "\tldq $1,24($27)\n");		\
  fprintf (FILE, "\tldq $27,16($27)\n");	\
  fprintf (FILE, "\tjmp $31,($27),0\n");	\
  fprintf (FILE, "\tnop\n");			\
  fprintf (FILE, "\t.quad 0,0\n");		\
}

/* Section in which to place the trampoline.  On Alpha, instructions
   may only be placed in a text segment.  */

#define TRAMPOLINE_SECTION text_section

/* Length in units of the trampoline for entering a nested function.  */

#define TRAMPOLINE_SIZE    32

/* Emit RTL insns to initialize the variable parts of a trampoline.
   FNADDR is an RTX for the address of the function's pure code.
   CXT is an RTX for the static chain value for the function.  We assume
   here that a function will be called many more times than its address
   is taken (e.g., it might be passed to qsort), so we take the trouble 
   to initialize the "hint" field in the JMP insn.  Note that the hint
   field is PC (new) + 4 * bits 13:0.  */

#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)			\
{									\
  rtx _temp, _temp1, _addr;						\
									\
  _addr = memory_address (Pmode, plus_constant ((TRAMP), 16));		\
  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (FNADDR));		\
  _addr = memory_address (Pmode, plus_constant ((TRAMP), 24));		\
  emit_move_insn (gen_rtx (MEM, Pmode, _addr), (CXT));			\
									\
  _temp = force_operand (plus_constant ((TRAMP), 12), NULL_RTX);	\
  _temp = expand_binop (DImode, sub_optab, (FNADDR), _temp, _temp, 1,	\
			OPTAB_WIDEN);					\
  _temp = expand_shift (RSHIFT_EXPR, Pmode, _temp,			\
			build_int_2 (2, 0), NULL_RTX, 1);		\
  _temp = expand_and (gen_lowpart (SImode, _temp),			\
		      GEN_INT (0x3fff), 0); 				\
									\
  _addr = memory_address (SImode, plus_constant ((TRAMP), 8));		\
  _temp1 = force_reg (SImode, gen_rtx (MEM, SImode, _addr));		\
  _temp1 = expand_and (_temp1, GEN_INT (0xffffc000), NULL_RTX);		\
  _temp1 = expand_binop (SImode, ior_optab, _temp1, _temp, _temp1, 1,	\
			 OPTAB_WIDEN);					\
									\
  emit_move_insn (gen_rtx (MEM, SImode, _addr), _temp1);		\
									\
  emit_library_call (gen_rtx (SYMBOL_REF, Pmode,			\
			      "__enable_execute_stack"),		\
		     0, VOIDmode, 1,_addr, Pmode);			\
									\
  emit_insn (gen_rtx (UNSPEC_VOLATILE, VOIDmode,			\
		      gen_rtvec (1, const0_rtx), 0));			\
}

/* Attempt to turn on access permissions for the stack.  */

#define TRANSFER_FROM_TRAMPOLINE					\
									\
void									\
__enable_execute_stack (addr)						\
     void *addr;							\
{									\
  long size = getpagesize ();						\
  long mask = ~(size-1);						\
  char *page = (char *) (((long) addr) & mask);				\
  char *end  = (char *) ((((long) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
									\
  /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */				\
  if (mprotect (page, end - page, 7) < 0)				\
    perror ("mprotect of trampoline code");				\
}

/* A C expression whose value is RTL representing the value of the return
   address for the frame COUNT steps up from the current frame.
   FRAMEADDR is the frame pointer of the COUNT frame, or the frame pointer of
   the COUNT-1 frame if RETURN_ADDR_IN_PREVIOUS_FRAME} is defined.  */

#define RETURN_ADDR_RTX(COUNT, FRAME)					\
  ((COUNT) == 0 ? alpha_return_addr() : const0_rtx)
extern struct rtx_def *alpha_return_addr ();

/* Addressing modes, and classification of registers for them.  */

/* #define HAVE_POST_INCREMENT */
/* #define HAVE_POST_DECREMENT */

/* #define HAVE_PRE_DECREMENT */
/* #define HAVE_PRE_INCREMENT */

/* Macros to check register numbers against specific register classes.  */

/* These assume that REGNO is a hard or pseudo reg number.
   They give nonzero only if REGNO is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   Since they use reg_renumber, they are safe only once reg_renumber
   has been allocated, which happens in local-alloc.c.  */

#define REGNO_OK_FOR_INDEX_P(REGNO) 0
#define REGNO_OK_FOR_BASE_P(REGNO) \
((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32  \
 || (REGNO) == 63 || reg_renumber[REGNO] == 63)

/* Maximum number of registers that can appear in a valid memory address.  */
#define MAX_REGS_PER_ADDRESS 1

/* Recognize any constant value that is a valid address.  For the Alpha,
   there are only constants none since we want to use LDA to load any
   symbolic addresses into registers.  */

#define CONSTANT_ADDRESS_P(X)   \
  (GET_CODE (X) == CONST_INT	\
   && (unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)

/* Include all constant integers and constant doubles, but not
   floating-point, except for floating-point zero.  */

#define LEGITIMATE_CONSTANT_P(X)  		\
  (GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT	\
   || (X) == CONST0_RTX (GET_MODE (X)))

/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
   and check its validity for a certain class.
   We have two alternate definitions for each of them.
   The usual definition accepts all pseudo regs; the other rejects
   them unless they have been allocated suitable hard regs.
   The symbol REG_OK_STRICT causes the latter definition to be used.

   Most source files want to accept pseudo regs in the hope that
   they will get allocated to the class that the insn wants them to be in.
   Source files for reload pass need to be strict.
   After reload, it makes no difference, since pseudo regs have
   been eliminated by then.  */

#ifndef REG_OK_STRICT

/* Nonzero if X is a hard reg that can be used as an index
   or if it is a pseudo reg.  */
#define REG_OK_FOR_INDEX_P(X) 0
/* Nonzero if X is a hard reg that can be used as a base reg
   or if it is a pseudo reg.  */
#define REG_OK_FOR_BASE_P(X)  \
  (REGNO (X) < 32 || REGNO (X) == 63 || REGNO (X) >= FIRST_PSEUDO_REGISTER)

#else

/* Nonzero if X is a hard reg that can be used as an index.  */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as a base reg.  */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))

#endif

/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
   that is a valid memory address for an instruction.
   The MODE argument is the machine mode for the MEM expression
   that wants to use this address. 

   For Alpha, we have either a constant address or the sum of a register
   and a constant address, or just a register.  For DImode, any of those
   forms can be surrounded with an AND that clear the low-order three bits;
   this is an "unaligned" access.

   First define the basic valid address.  */

#define GO_IF_LEGITIMATE_SIMPLE_ADDRESS(MODE, X, ADDR) \
{ if (REG_P (X) && REG_OK_FOR_BASE_P (X))	\
    goto ADDR;					\
  if (CONSTANT_ADDRESS_P (X))			\
    goto ADDR;					\
  if (GET_CODE (X) == PLUS			\
      && REG_P (XEXP (X, 0))			\
      && REG_OK_FOR_BASE_P (XEXP (X, 0))	\
      && CONSTANT_ADDRESS_P (XEXP (X, 1)))	\
    goto ADDR;					\