elxsi.md

GCC编译器源代码

  "cmpu.8\\t%0,%1,%2:ge")

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
	(gt (match_operand:QI 1 "register_operand" "r")
	    (match_operand:QI 2 "general_operand" "m")))]
  ""
  "cmp.8\\t%0,%1,%2:gt")

(define_insn ""
  [(set (match_operand:QI 0 "register_operand" "=r")
	(gtu (match_operand:QI 1 "register_operand" "r")
	    (match_operand:QI 2 "general_operand" "m")))]
  ""
  "cmpu.8\\t%0,%1,%2:gt")



(define_insn "movdf"  [(set (match_operand:DF 0 "general_operand" "=r,m")
	(match_operand:DF 1 "general_operand" "rm,r"))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.64\\t%0,%1\";
  return \"st.64\\t%1,%0\";
}")

(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=r,m")
	(match_operand:SF 1 "general_operand" "rm,r"))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.32\\t%0,%1\";
  return \"st.32\\t%1,%0\";
}")

(define_insn "movdi"
  [(set (match_operand:DI 0 "general_operand" "=r,m,rm")
	(match_operand:DI 1 "general_operand" "g,r,I"))]
  ""
  "*
  if (which_alternative == 0)
    return \"ld.64\\t%0,%1\";
  else if (which_alternative == 1)
    return \"st.64\\t%1,%0\";
  else
    if (GET_CODE(operands[1])==CONST_INT) {
      if (INTVAL(operands[1]) >= 0)
        return \"sti.64\\t%c1,%0\";
      else
        return \"stin.64\\t%n1,%0\";
    }
")

(define_insn "movsi"
  [(set (match_operand:SI 0 "general_operand" "=r,m,r")
	(match_operand:SI 1 "general_operand" "rm,rI,i"))]
  ""
  "*
  if (which_alternative == 0)
    return \"ld.32\\t%0,%1\";
  else if (which_alternative == 1) {
    if (GET_CODE(operands[1])==CONST_INT) {
      if (INTVAL(operands[1]) >= 0)
        return \"sti.32\\t%c1,%0\";
      else
        return \"stin.32\\t%n1,%0\";
    }
    return \"st.32\\t%1,%0\";
  } else
    return \"ld.64\\t%0,%1 ; I only want 32\";
")

(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
	(match_operand:HI 1 "general_operand" "m,rI,ri"))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.16\\t%0,%1\";
  if (which_alternative == 2)
    return \"ld.64\\t%0,%1\\t; I only want 16\";
  if (GET_CODE(operands[1])==CONST_INT) {
    if (INTVAL(operands[1]) >= 0)
      return \"sti.16\\t%c1,%0\";
    else
      return \"stin.16\\t%n1,%0\";
  }
  return \"st.16\\t%1,%0\";
}")

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
	(match_operand:QI 1 "general_operand" "m,rI,ri"))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.8\\t%0,%1\";
  if (which_alternative == 2)
    return \"ld.64\\t%0,%1\\t; I only want 8\";
  if (GET_CODE(operands[1])==CONST_INT) {
    if (INTVAL(operands[1]) >= 0)
      return \"sti.8\\t%c1,%0\";
    else
      return \"stin.8\\t%n1,%0\";
  }
  return \"st.8\\t%1,%0\";
}")

;; Extension and truncation insns.
;; Those for integer source operand
;; are ordered widest source type first.

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(truncate:SF (match_operand:DF 1 "general_operand" "rm")))]
  ""
  "cvt.ds\\t%0,%1")

(define_insn "truncdiqi2"
  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
	(truncate:QI (match_operand:DI 1 "general_operand" "m,r,0")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.8\\t%0,%1\";
  else if (which_alternative == 1)
    return \"st.8\\t%1,%0\";
  return \"\";
}")

(define_insn "truncdihi2"
  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
	(truncate:HI (match_operand:DI 1 "general_operand" "m,r,0")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.16\\t%0,%1\";
  if (which_alternative == 1)
    return \"st.16\\t%1,%0\";
  return \"\";
}")

(define_insn "truncdisi2"
  [(set (match_operand:SI 0 "general_operand" "=r,m")
	(truncate:SI (match_operand:DI 1 "general_operand" "rm,r")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.32\\t%0,%1\";
  return \"st.32\\t%1,%0\";
}")

(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
	(truncate:QI (match_operand:SI 1 "general_operand" "m,r,0")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.8\\t%0,%1\";
  if (which_alternative == 1)
    return \"st.8\\t%1,%0\";
  return \"\";
}")

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "general_operand" "=r,m,r")
	(truncate:HI (match_operand:SI 1 "general_operand" "m,r,0")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.16\\t%0,%1\";
  if (which_alternative == 1)
    return \"st.16\\t%1,%0\";
  return \"\";
}")

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "general_operand" "=r,m,r")
	(truncate:QI (match_operand:HI 1 "general_operand" "m,r,0")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"ld.8\\t%0,%1\";
  if (which_alternative == 1)
    return \"st.8\\t%1,%0\";
  return \"\";
}")

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(sign_extend:DF (match_operand:SF 1 "general_operand" "rm")))]
  ""
  "cvt.sd\\t%0,%1")

(define_insn "extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(sign_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
  ""
  "ld.32\\t%0,%1")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ld.16\\t%0,%1\";
     return \"extract\\t%0,%1:bit 48,16\";
")

(define_insn "extendhidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(sign_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ld.16\\t%0,%1\";
     return \"extract\\t%0,%1:bit 48,16\";
")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ld.8\\t%0,%1\";
     return \"extract\\t%0,%1:bit 56,8\";
")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ld.8\\t%0,%1\";
     return \"extract\\t%0,%1:bit 56,8\";
")

(define_insn "extendqidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(sign_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ld.8\\t%0,%1\";
     return \"extract\\t%0,%1:bit 56,8\";
")

(define_insn "zero_extendsidi2"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
  ""
  "ldz.32\\t%0,%1")


(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ldz.16\\t%0,%1\";
     return \"extractz\\t%0,%1:bit 48,16\";
")

(define_insn "zero_extendhidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(zero_extend:DI (match_operand:HI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ldz.16\\t%0,%1\";
     return \"extractz\\t%0,%1:bit 48,16\";
")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ldz.8\\t%0,%1\";
     return \"extractz\\t%0,%1:bit 56,8\";
")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ldz.8\\t%0,%1\";
     return \"extractz\\t%0,%1:bit 56,8\";
")

(define_insn "zero_extendqidi2"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(zero_extend:DI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
     if (which_alternative==0)
       return \"ldz.8\\t%0,%1\";
     return \"extractz\\t%0,%1:bit 56,8\";
")


(define_insn "ashrdi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand:SI 2 "general_operand" "rn")))]
  ""
  "sra\\t%0,%1,%2")

(define_insn "lshrdi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(lshiftrt:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand:SI 2 "general_operand" "rn")))]
  ""
  "srl\\t%0,%1,%2")

(define_insn "ashldi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashift:DI (match_operand:DI 1 "register_operand" "r")
		   (match_operand:SI 2 "general_operand" "rn")))]
  ""
  "sla\\t%0,%1,%2")

(define_insn "anddi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(and:DI (match_operand:DI 1 "general_operand" "%0,r")
		(match_operand:DI 2 "general_operand" "g,g")))]
  "1 /*which_alternative == 0 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"and\\t%0,%2\";
    return \"and\\t%0,%1,%2\";
")

(define_insn "iordi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(ior:DI (match_operand:DI 1 "general_operand" "%0,r")
		(match_operand:DI 2 "general_operand" "g,g")))]
  "1 /*which_alternative == 0 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"or\\t%0,%2\";
    return \"or\\t%0,%1,%2\";
")

(define_insn "xordi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(xor:DI (match_operand:DI 1 "general_operand" "%0,r")
		(match_operand:DI 2 "general_operand" "g,g")))]
  "1 /*which_alternative == 0 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"xor\\t%0,%2\";
    return \"xor\\t%0,%1,%2\";
")

(define_insn "one_cmpldi2"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(not:DI (match_operand:DI 1 "general_operand" "rm")))]
  ""
  "not\\t%0,%1")

;; gcc 2.1 does not widen ~si into ~di.
(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(not:SI (match_operand:SI 1 "register_operand" "r")))]
  ""
  "not\\t%0,%1")

(define_insn "negdi2"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(neg:DI (match_operand:DI 1 "general_operand" "rm")))]
  ""
  "neg.64\\t%0,%1")

(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(neg:SI (match_operand:SI 1 "general_operand" "m,r")))]
  ""
  "*
    if (which_alternative == 0)
      return \"neg.32\\t%0,%1\";
    return \"neg.64\\t%0,%1 ; I only want 32\";
")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(neg:HI (match_operand:HI 1 "general_operand" "m,r")))]
  ""
  "*
    if (which_alternative == 0)
      return \"neg.16\\t%0,%1\";
    return \"neg.64\\t%0,%1 ; I only want 16\";
")

(define_insn "adddf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(plus:DF (match_operand:DF 1 "general_operand" "%0")
		  (match_operand:DF 2 "general_operand" "rm")))]
  ""
  "fadd.64\\t%0,%2")

(define_insn "addsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(plus:SF (match_operand:SF 1 "general_operand" "%0")
		 (match_operand:SF 2 "general_operand" "rm")))]
  ""
  "fadd.32\\t%0,%2")

;; There is also an addi.64  4,.r0'' optimization
(define_insn "adddi3"
  [(set (match_operand:DI 0 "register_operand" "=r,r")
	(plus:DI (match_operand:DI 1 "general_operand" "%0,r")
		 (match_operand:DI 2 "general_operand" "g,g")))]
  "1 /*which_alternative == 0 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"add.64\\t%0,%2\";
    return \"add.64\\t%0,%1,%2\";
")

(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(plus:SI (match_operand:SI 1 "general_operand" "%0,r,0")
		 (match_operand:SI 2 "general_operand" "m,m,g")))]
  "1 /*which_alternative != 1 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"add.32\\t%0,%2\";
    if (which_alternative == 1)
      return \"add.32\\t%0,%1,%2\";
    return \"add.64\\t%0,%2 ; I only want 32\";
")

(define_insn "addhi3"
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
	(plus:HI (match_operand:HI 1 "general_operand" "%0,r,0")
		 (match_operand:HI 2 "general_operand" "m,m,g")))]
  "1 /*which_alternative != 1 || check356(operands[2])*/"
  "*
    if (which_alternative == 0)
      return \"add.16\\t%0,%2\";
    if (which_alternative == 1)
      return \"add.16\\t%0,%1,%2\";
    return \"add.64\\t%0,%2 ; I only want 16\";
")

(define_insn "subdf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(minus:DF (match_operand:DF 1 "general_operand" "0")
		  (match_operand:DF 2 "general_operand" "rm")))]
  ""
  "fsub.64\\t%0,%2")

(define_insn "subsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")