sin.tan.qmsg

正弦信号数据发生器

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register tmp\[4\] register d\[5\]~reg0 314.76 MHz 3.177 ns Internal " "Info: Clock \"clk\" has Internal fmax of 314.76 MHz between source register \"tmp\[4\]\" and destination register \"d\[5\]~reg0\" (period= 3.177 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.953 ns + Longest register register " "Info: + Longest register to register delay is 2.953 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmp\[4\] 1 REG LCFF_X14_Y3_N19 19 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y3_N19; Fanout = 19; REG Node = 'tmp\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmp[4] } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.909 ns) + CELL(0.319 ns) 1.228 ns Mux2~153 2 COMB LCCOMB_X15_Y3_N22 2 " "Info: 2: + IC(0.909 ns) + CELL(0.319 ns) = 1.228 ns; Loc. = LCCOMB_X15_Y3_N22; Fanout = 2; COMB Node = 'Mux2~153'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.228 ns" { tmp[4] Mux2~153 } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.832 ns) + CELL(0.178 ns) 2.238 ns Mux2~155 3 COMB LCCOMB_X13_Y3_N16 1 " "Info: 3: + IC(0.832 ns) + CELL(0.178 ns) = 2.238 ns; Loc. = LCCOMB_X13_Y3_N16; Fanout = 1; COMB Node = 'Mux2~155'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.010 ns" { Mux2~153 Mux2~155 } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.322 ns) 2.857 ns Mux2~157 4 COMB LCCOMB_X13_Y3_N24 1 " "Info: 4: + IC(0.297 ns) + CELL(0.322 ns) = 2.857 ns; Loc. = LCCOMB_X13_Y3_N24; Fanout = 1; COMB Node = 'Mux2~157'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.619 ns" { Mux2~155 Mux2~157 } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.953 ns d\[5\]~reg0 5 REG LCFF_X13_Y3_N25 1 " "Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 2.953 ns; Loc. = LCFF_X13_Y3_N25; Fanout = 1; REG Node = 'd\[5\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Mux2~157 d[5]~reg0 } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.915 ns ( 30.99 % ) " "Info: Total cell delay = 0.915 ns ( 30.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.038 ns ( 69.01 % ) " "Info: Total interconnect delay = 2.038 ns ( 69.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.953 ns" { tmp[4] Mux2~153 Mux2~155 Mux2~157 d[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.953 ns" { tmp[4] {} Mux2~153 {} Mux2~155 {} Mux2~157 {} d[5]~reg0 {} } { 0.000ns 0.909ns 0.832ns 0.297ns 0.000ns } { 0.000ns 0.319ns 0.178ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.015 ns - Smallest " "Info: - Smallest clock skew is 0.015 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.576 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.576 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.602 ns) 2.576 ns d\[5\]~reg0 3 REG LCFF_X13_Y3_N25 1 " "Info: 3: + IC(0.776 ns) + CELL(0.602 ns) = 2.576 ns; Loc. = LCFF_X13_Y3_N25; Fanout = 1; REG Node = 'd\[5\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.378 ns" { clk~clkctrl d[5]~reg0 } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.75 % ) " "Info: Total cell delay = 1.668 ns ( 64.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.908 ns ( 35.25 % ) " "Info: Total interconnect delay = 0.908 ns ( 35.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.576 ns" { clk clk~clkctrl d[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.576 ns" { clk {} clk~combout {} clk~clkctrl {} d[5]~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.776ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.561 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.761 ns) + CELL(0.602 ns) 2.561 ns tmp\[4\] 3 REG LCFF_X14_Y3_N19 19 " "Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N19; Fanout = 19; REG Node = 'tmp\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.363 ns" { clk~clkctrl tmp[4] } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 65.13 % ) " "Info: Total cell delay = 1.668 ns ( 65.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.893 ns ( 34.87 % ) " "Info: Total interconnect delay = 0.893 ns ( 34.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl tmp[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} tmp[4] {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.576 ns" { clk clk~clkctrl d[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.576 ns" { clk {} clk~combout {} clk~clkctrl {} d[5]~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.776ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl tmp[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} tmp[4] {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.953 ns" { tmp[4] Mux2~153 Mux2~155 Mux2~157 d[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.953 ns" { tmp[4] {} Mux2~153 {} Mux2~155 {} Mux2~157 {} d[5]~reg0 {} } { 0.000ns 0.909ns 0.832ns 0.297ns 0.000ns } { 0.000ns 0.319ns 0.178ns 0.322ns 0.096ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.576 ns" { clk clk~clkctrl d[5]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.576 ns" { clk {} clk~combout {} clk~clkctrl {} d[5]~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.776ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl tmp[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} tmp[4] {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "tmp\[0\] clr clk 0.659 ns register " "Info: tsu for register \"tmp\[0\]\" (data pin = \"clr\", clock pin = \"clk\") is 0.659 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.258 ns + Longest pin register " "Info: + Longest pin to register delay is 3.258 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns clr 1 PIN PIN_24 7 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'clr'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.758 ns) 3.258 ns tmp\[0\] 2 REG LCFF_X14_Y3_N11 22 " "Info: 2: + IC(1.444 ns) + CELL(0.758 ns) = 3.258 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.202 ns" { clr tmp[0] } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.814 ns ( 55.68 % ) " "Info: Total cell delay = 1.814 ns ( 55.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.444 ns ( 44.32 % ) " "Info: Total interconnect delay = 1.444 ns ( 44.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.258 ns" { clr tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.258 ns" { clr {} clr~combout {} tmp[0] {} } { 0.000ns 0.000ns 1.444ns } { 0.000ns 1.056ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.561 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.761 ns) + CELL(0.602 ns) 2.561 ns tmp\[0\] 3 REG LCFF_X14_Y3_N11 22 " "Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.363 ns" { clk~clkctrl tmp[0] } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 65.13 % ) " "Info: Total cell delay = 1.668 ns ( 65.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.893 ns ( 34.87 % ) " "Info: Total interconnect delay = 0.893 ns ( 34.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} tmp[0] {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.258 ns" { clr tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.258 ns" { clr {} clr~combout {} tmp[0] {} } { 0.000ns 0.000ns 1.444ns } { 0.000ns 1.056ns 0.758ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} tmp[0] {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk d\[1\] d\[1\]~reg0 8.162 ns register " "Info: tco from clock \"clk\" to destination pin \"d\[1\]\" through register \"d\[1\]~reg0\" is 8.162 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.561 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.761 ns) + CELL(0.602 ns) 2.561 ns d\[1\]~reg0 3 REG LCFF_X14_Y3_N9 1 " "Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N9; Fanout = 1; REG Node = 'd\[1\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.363 ns" { clk~clkctrl d[1]~reg0 } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 65.13 % ) " "Info: Total cell delay = 1.668 ns ( 65.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.893 ns ( 34.87 % ) " "Info: Total interconnect delay = 0.893 ns ( 34.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl d[1]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} d[1]~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.324 ns + Longest register pin " "Info: + Longest register to pin delay is 5.324 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d\[1\]~reg0 1 REG LCFF_X14_Y3_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y3_N9; Fanout = 1; REG Node = 'd\[1\]~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { d[1]~reg0 } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.268 ns) + CELL(3.056 ns) 5.324 ns d\[1\] 2 PIN PIN_181 0 " "Info: 2: + IC(2.268 ns) + CELL(3.056 ns) = 5.324 ns; Loc. = PIN_181; Fanout = 0; PIN Node = 'd\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.324 ns" { d[1]~reg0 d[1] } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 57.40 % ) " "Info: Total cell delay = 3.056 ns ( 57.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.268 ns ( 42.60 % ) " "Info: Total interconnect delay = 2.268 ns ( 42.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.324 ns" { d[1]~reg0 d[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.324 ns" { d[1]~reg0 {} d[1] {} } { 0.000ns 2.268ns } { 0.000ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl d[1]~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} d[1]~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.324 ns" { d[1]~reg0 d[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.324 ns" { d[1]~reg0 {} d[1] {} } { 0.000ns 2.268ns } { 0.000ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "tmp\[0\] clr clk -0.411 ns register " "Info: th for register \"tmp\[0\]\" (data pin = \"clr\", clock pin = \"clk\") is -0.411 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.561 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.761 ns) + CELL(0.602 ns) 2.561 ns tmp\[0\] 3 REG LCFF_X14_Y3_N11 22 " "Info: 3: + IC(0.761 ns) + CELL(0.602 ns) = 2.561 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.363 ns" { clk~clkctrl tmp[0] } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 65.13 % ) " "Info: Total cell delay = 1.668 ns ( 65.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.893 ns ( 34.87 % ) " "Info: Total interconnect delay = 0.893 ns ( 34.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} tmp[0] {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.258 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.258 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns clr 1 PIN PIN_24 7 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 7; PIN Node = 'clr'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.444 ns) + CELL(0.758 ns) 3.258 ns tmp\[0\] 2 REG LCFF_X14_Y3_N11 22 " "Info: 2: + IC(1.444 ns) + CELL(0.758 ns) = 3.258 ns; Loc. = LCFF_X14_Y3_N11; Fanout = 22; REG Node = 'tmp\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.202 ns" { clr tmp[0] } "NODE_NAME" } } { "sin.Vhd" "" { Text "D:/CPLD开发训练/sina/sin.Vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.814 ns ( 55.68 % ) " "Info: Total cell delay = 1.814 ns ( 55.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.444 ns ( 44.32 % ) " "Info: Total interconnect delay = 1.444 ns ( 44.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.258 ns" { clr tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.258 ns" { clr {} clr~combout {} tmp[0] {} } { 0.000ns 0.000ns 1.444ns } { 0.000ns 1.056ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk clk~clkctrl tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.561 ns" { clk {} clk~combout {} clk~clkctrl {} tmp[0] {} } { 0.000ns 0.000ns 0.132ns 0.761ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.258 ns" { clr tmp[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.258 ns" { clr {} clr~combout {} tmp[0] {} } { 0.000ns 0.000ns 1.444ns } { 0.000ns 1.056ns 0.758ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}