pulse.hier_info

脉冲发生器

|pulse
clock => counter:u2.clk
clock => c.CLK
clock => counter:u1.clk
load => pr.IN1
counter_able => en_in.IN1
h_data[0] => counter:u1.data[0]
h_data[1] => counter:u1.data[1]
h_data[2] => counter:u1.data[2]
h_data[3] => counter:u1.data[3]
h_data[4] => counter:u1.data[4]
h_data[5] => counter:u1.data[5]
h_data[6] => counter:u1.data[6]
h_data[7] => counter:u1.data[7]
l_data[0] => counter:u2.data[0]
l_data[1] => counter:u2.data[1]
l_data[2] => counter:u2.data[2]
l_data[3] => counter:u2.data[3]
l_data[4] => counter:u2.data[4]
l_data[5] => counter:u2.data[5]
l_data[6] => counter:u2.data[6]
l_data[7] => counter:u2.data[7]
channel <= counter:u1.co


|pulse|counter:u1
clk => q[7]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => pulse.CLK
enable => q~7.OUTPUTSELECT
enable => q~6.OUTPUTSELECT
enable => q~5.OUTPUTSELECT
enable => q~4.OUTPUTSELECT
enable => q~3.OUTPUTSELECT
enable => q~2.OUTPUTSELECT
enable => q~1.OUTPUTSELECT
enable => q~0.OUTPUTSELECT
load => q[7]~reg0.ALOAD
load => q[6]~reg0.ALOAD
load => q[5]~reg0.ALOAD
load => q[4]~reg0.ALOAD
load => q[3]~reg0.ALOAD
load => q[2]~reg0.ALOAD
load => q[1]~reg0.ALOAD
load => q[0]~reg0.ALOAD
load => pulse.ENA
co <= pulse.DB_MAX_OUTPUT_PORT_TYPE
data[0] => q[0]~reg0.ADATA
data[1] => q[1]~reg0.ADATA
data[2] => q[2]~reg0.ADATA
data[3] => q[3]~reg0.ADATA
data[4] => q[4]~reg0.ADATA
data[5] => q[5]~reg0.ADATA
data[6] => q[6]~reg0.ADATA
data[7] => q[7]~reg0.ADATA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|pulse|counter:u2
clk => q[7]~reg0.CLK
clk => q[6]~reg0.CLK
clk => q[5]~reg0.CLK
clk => q[4]~reg0.CLK
clk => q[3]~reg0.CLK
clk => q[2]~reg0.CLK
clk => q[1]~reg0.CLK
clk => q[0]~reg0.CLK
clk => pulse.CLK
enable => q~7.OUTPUTSELECT
enable => q~6.OUTPUTSELECT
enable => q~5.OUTPUTSELECT
enable => q~4.OUTPUTSELECT
enable => q~3.OUTPUTSELECT
enable => q~2.OUTPUTSELECT
enable => q~1.OUTPUTSELECT
enable => q~0.OUTPUTSELECT
load => q[7]~reg0.ALOAD
load => q[6]~reg0.ALOAD
load => q[5]~reg0.ALOAD
load => q[4]~reg0.ALOAD
load => q[3]~reg0.ALOAD
load => q[2]~reg0.ALOAD
load => q[1]~reg0.ALOAD
load => q[0]~reg0.ALOAD
load => pulse.ENA
co <= pulse.DB_MAX_OUTPUT_PORT_TYPE
data[0] => q[0]~reg0.ADATA
data[1] => q[1]~reg0.ADATA
data[2] => q[2]~reg0.ADATA
data[3] => q[3]~reg0.ADATA
data[4] => q[4]~reg0.ADATA
data[5] => q[5]~reg0.ADATA
data[6] => q[6]~reg0.ADATA
data[7] => q[7]~reg0.ADATA
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE