prev_cmp_pulse.map.qmsg

脉冲发生器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Mar 15 17:24:16 2008 " "Info: Processing started: Sat Mar 15 17:24:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pulse -c pulse " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pulse -c pulse" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "counter.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file counter.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 counter-counter_behave " "Info: Found design unit 1: counter-counter_behave" {  } { { "counter.vhd" "" { Text "C:/altera/72/quartus/pulse/counter.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.vhd" "" { Text "C:/altera/72/quartus/pulse/counter.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pulse.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pulse.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pulse-pulse_behave " "Info: Found design unit 1: pulse-pulse_behave" {  } { { "pulse.vhd" "" { Text "C:/altera/72/quartus/pulse/pulse.vhd" 15 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 pulse " "Info: Found entity 1: pulse" {  } { { "pulse.vhd" "" { Text "C:/altera/72/quartus/pulse/pulse.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "andgate.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file andgate.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 andgate-andgate_behave " "Info: Found design unit 1: andgate-andgate_behave" {  } { { "andgate.vhd" "" { Text "C:/altera/72/quartus/pulse/andgate.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 andgate " "Info: Found entity 1: andgate" {  } { { "andgate.vhd" "" { Text "C:/altera/72/quartus/pulse/andgate.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pulse " "Info: Elaborating entity \"pulse\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "inter2 pulse.vhd(27) " "Warning (10036): Verilog HDL or VHDL warning at pulse.vhd(27): object \"inter2\" assigned a value but never read" {  } { { "pulse.vhd" "" { Text "C:/altera/72/quartus/pulse/pulse.vhd" 27 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:u1 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:u1\"" {  } { { "pulse.vhd" "u1" { Text "C:/altera/72/quartus/pulse/pulse.vhd" 30 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "load counter.vhd(20) " "Warning (10492): VHDL Process Statement warning at counter.vhd(20): signal \"load\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter.vhd" "" { Text "C:/altera/72/quartus/pulse/counter.vhd" 20 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data counter.vhd(21) " "Warning (10492): VHDL Process Statement warning at counter.vhd(21): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "counter.vhd" "" { Text "C:/altera/72/quartus/pulse/counter.vhd" 21 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "78 " "Info: Implemented 78 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "19 " "Info: Implemented 19 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "58 " "Info: Implemented 58 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Allocated 159 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Mar 15 17:24:21 2008 " "Info: Processing ended: Sat Mar 15 17:24:21 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}