lianglu.map.rpt

该程序可是多路频率检测

; PowerPlay Power Optimization                                                   ; Normal compilation ; Normal compilation ;
; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                              ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                 ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+
; lianglu.vhd                      ; yes             ; User VHDL File  ; D:/CPLD开发训练/863Lianglujiance/lianglu.vhd ;
+----------------------------------+-----------------+-----------------+----------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 44    ;
;                                             ;       ;
; Total combinational functions               ; 30    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 4     ;
;     -- 3 input functions                    ; 2     ;
;     -- <=2 input functions                  ; 24    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 8     ;
;     -- arithmetic mode                      ; 22    ;
;                                             ;       ;
; Total registers                             ; 44    ;
;     -- Dedicated logic registers            ; 44    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 7     ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 24    ;
; Total fan-out                               ; 230   ;
; Average fan-out                             ; 2.84  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |lianglu                   ; 30 (30)           ; 44 (44)      ; 0           ; 0            ; 0       ; 0         ; 7    ; 0            ; |lianglu            ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Registers Removed During Synthesis                         ;
+---------------------------------------+--------------------+
; Register name                         ; Reason for Removal ;
+---------------------------------------+--------------------+
; X1[0..2]                              ; Lost fanout        ;
; X2[0..2]                              ; Lost fanout        ;
; Total Number of Removed Registers = 6 ;                    ;
+---------------------------------------+--------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 44    ;
; Number of registers using Synchronous Clear  ; 24    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 24    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 24    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Mar 14 22:35:15 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lianglu -c lianglu
Info: Found 2 design units, including 1 entities, in source file lianglu.vhd
    Info: Found design unit 1: lianglu-ONE
    Info: Found entity 1: lianglu
Info: Elaborating entity "lianglu" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at lianglu.vhd(28): signal "DCLK1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lianglu.vhd(41): signal "DCLK2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lianglu.vhd(46): signal "LOAD1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at lianglu.vhd(55): signal "LOAD2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: 6 registers lost all their fanouts during netlist optimizations. The first 6 are displayed below.
    Info: Register "X1[0]" lost all its fanouts during netlist optimizations.
    Info: Register "X1[1]" lost all its fanouts during netlist optimizations.
    Info: Register "X1[2]" lost all its fanouts during netlist optimizations.
    Info: Register "X2[0]" lost all its fanouts during netlist optimizations.
    Info: Register "X2[1]" lost all its fanouts during netlist optimizations.
    Info: Register "X2[2]" lost all its fanouts during netlist optimizations.
Info: Implemented 55 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 2 output pins
    Info: Implemented 48 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Fri Mar 14 22:35:19 2008
    Info: Elapsed time: 00:00:04