prev_cmp_lianglu.tan.qmsg

该程序可是多路频率检测

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "DCLK2 register X2\[10\] register M2~reg0 239.23 MHz 4.18 ns Internal " "Info: Clock \"DCLK2\" has Internal fmax of 239.23 MHz between source register \"X2\[10\]\" and destination register \"M2~reg0\" (period= 4.18 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.941 ns + Longest register register " "Info: + Longest register to register delay is 3.941 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns X2\[10\] 1 REG LCFF_X21_Y12_N29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y12_N29; Fanout = 1; REG Node = 'X2\[10\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { X2[10] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.939 ns) + CELL(0.178 ns) 2.117 ns LessThan1~276 2 COMB LCCOMB_X25_Y3_N0 1 " "Info: 2: + IC(1.939 ns) + CELL(0.178 ns) = 2.117 ns; Loc. = LCCOMB_X25_Y3_N0; Fanout = 1; COMB Node = 'LessThan1~276'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.117 ns" { X2[10] LessThan1~276 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1630 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.550 ns) + CELL(0.178 ns) 3.845 ns LessThan1~279 3 COMB LCCOMB_X21_Y12_N0 1 " "Info: 3: + IC(1.550 ns) + CELL(0.178 ns) = 3.845 ns; Loc. = LCCOMB_X21_Y12_N0; Fanout = 1; COMB Node = 'LessThan1~279'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.728 ns" { LessThan1~276 LessThan1~279 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1630 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 3.941 ns M2~reg0 4 REG LCFF_X21_Y12_N1 1 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 3.941 ns; Loc. = LCFF_X21_Y12_N1; Fanout = 1; REG Node = 'M2~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LessThan1~279 M2~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.452 ns ( 11.47 % ) " "Info: Total cell delay = 0.452 ns ( 11.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.489 ns ( 88.53 % ) " "Info: Total interconnect delay = 3.489 ns ( 88.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.941 ns" { X2[10] LessThan1~276 LessThan1~279 M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.941 ns" { X2[10] {} LessThan1~276 {} LessThan1~279 {} M2~reg0 {} } { 0.000ns 1.939ns 1.550ns 0.000ns } { 0.000ns 0.178ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK2 destination 2.584 ns + Shortest register " "Info: + Shortest clock path from clock \"DCLK2\" to destination register is 2.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns DCLK2 1 CLK PIN_27 13 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_27; Fanout = 13; CLK Node = 'DCLK2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK2 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns DCLK2~clkctrl 2 COMB CLKCTRL_G3 13 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'DCLK2~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK2 DCLK2~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.602 ns) 2.584 ns M2~reg0 3 REG LCFF_X21_Y12_N1 1 " "Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X21_Y12_N1; Fanout = 1; REG Node = 'M2~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.386 ns" { DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.55 % ) " "Info: Total cell delay = 1.668 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.916 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.916 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} M2~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK2 source 2.584 ns - Longest register " "Info: - Longest clock path from clock \"DCLK2\" to source register is 2.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns DCLK2 1 CLK PIN_27 13 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_27; Fanout = 13; CLK Node = 'DCLK2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK2 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns DCLK2~clkctrl 2 COMB CLKCTRL_G3 13 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G3; Fanout = 13; COMB Node = 'DCLK2~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK2 DCLK2~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.602 ns) 2.584 ns X2\[10\] 3 REG LCFF_X21_Y12_N29 1 " "Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X21_Y12_N29; Fanout = 1; REG Node = 'X2\[10\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.386 ns" { DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.55 % ) " "Info: Total cell delay = 1.668 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.916 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.916 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} X2[10] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} M2~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} X2[10] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.941 ns" { X2[10] LessThan1~276 LessThan1~279 M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.941 ns" { X2[10] {} LessThan1~276 {} LessThan1~279 {} M2~reg0 {} } { 0.000ns 1.939ns 1.550ns 0.000ns } { 0.000ns 0.178ns 0.178ns 0.096ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} M2~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} X2[10] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Q1\[6\] ENA clk 5.767 ns register " "Info: tsu for register \"Q1\[6\]\" (data pin = \"ENA\", clock pin = \"clk\") is 5.767 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.357 ns + Longest pin register " "Info: + Longest pin to register delay is 8.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.893 ns) 0.893 ns ENA 1 PIN PIN_185 24 " "Info: 1: + IC(0.000 ns) + CELL(0.893 ns) = 0.893 ns; Loc. = PIN_185; Fanout = 24; PIN Node = 'ENA'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ENA } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.706 ns) + CELL(0.758 ns) 8.357 ns Q1\[6\] 2 REG LCFF_X19_Y6_N21 3 " "Info: 2: + IC(6.706 ns) + CELL(0.758 ns) = 8.357 ns; Loc. = LCFF_X19_Y6_N21; Fanout = 3; REG Node = 'Q1\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.464 ns" { ENA Q1[6] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.651 ns ( 19.76 % ) " "Info: Total cell delay = 1.651 ns ( 19.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.706 ns ( 80.24 % ) " "Info: Total interconnect delay = 6.706 ns ( 80.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.357 ns" { ENA Q1[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.357 ns" { ENA {} ENA~combout {} Q1[6] {} } { 0.000ns 0.000ns 6.706ns } { 0.000ns 0.893ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.552 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.552 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.602 ns) 2.552 ns Q1\[6\] 3 REG LCFF_X19_Y6_N21 3 " "Info: 3: + IC(0.752 ns) + CELL(0.602 ns) = 2.552 ns; Loc. = LCFF_X19_Y6_N21; Fanout = 3; REG Node = 'Q1\[6\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.354 ns" { clk~clkctrl Q1[6] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 65.36 % ) " "Info: Total cell delay = 1.668 ns ( 65.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.884 ns ( 34.64 % ) " "Info: Total interconnect delay = 0.884 ns ( 34.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.552 ns" { clk clk~clkctrl Q1[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.552 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[6] {} } { 0.000ns 0.000ns 0.132ns 0.752ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.357 ns" { ENA Q1[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.357 ns" { ENA {} ENA~combout {} Q1[6] {} } { 0.000ns 0.000ns 6.706ns } { 0.000ns 0.893ns 0.758ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.552 ns" { clk clk~clkctrl Q1[6] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.552 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[6] {} } { 0.000ns 0.000ns 0.132ns 0.752ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}