prev_cmp_lianglu.tan.qmsg

该程序可是多路频率检测

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register Q2\[0\] Q2\[11\] 380.08 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 380.08 MHz between source register \"Q2\[0\]\" and destination register \"Q2\[11\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.311 ns + Longest register register " "Info: + Longest register to register delay is 2.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q2\[0\] 1 REG LCFF_X21_Y12_N5 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y12_N5; Fanout = 3; REG Node = 'Q2\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q2[0] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.495 ns) 0.863 ns Q2\[0\]~135 2 COMB LCCOMB_X21_Y12_N4 2 " "Info: 2: + IC(0.368 ns) + CELL(0.495 ns) = 0.863 ns; Loc. = LCCOMB_X21_Y12_N4; Fanout = 2; COMB Node = 'Q2\[0\]~135'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.863 ns" { Q2[0] Q2[0]~135 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 0.943 ns Q2\[1\]~137 3 COMB LCCOMB_X21_Y12_N6 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 0.943 ns; Loc. = LCCOMB_X21_Y12_N6; Fanout = 2; COMB Node = 'Q2\[1\]~137'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[0]~135 Q2[1]~137 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.023 ns Q2\[2\]~139 4 COMB LCCOMB_X21_Y12_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.023 ns; Loc. = LCCOMB_X21_Y12_N8; Fanout = 2; COMB Node = 'Q2\[2\]~139'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[1]~137 Q2[2]~139 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.103 ns Q2\[3\]~141 5 COMB LCCOMB_X21_Y12_N10 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.103 ns; Loc. = LCCOMB_X21_Y12_N10; Fanout = 2; COMB Node = 'Q2\[3\]~141'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[2]~139 Q2[3]~141 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.183 ns Q2\[4\]~143 6 COMB LCCOMB_X21_Y12_N12 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 1.183 ns; Loc. = LCCOMB_X21_Y12_N12; Fanout = 2; COMB Node = 'Q2\[4\]~143'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[3]~141 Q2[4]~143 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 1.357 ns Q2\[5\]~145 7 COMB LCCOMB_X21_Y12_N14 2 " "Info: 7: + IC(0.000 ns) + CELL(0.174 ns) = 1.357 ns; Loc. = LCCOMB_X21_Y12_N14; Fanout = 2; COMB Node = 'Q2\[5\]~145'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Q2[4]~143 Q2[5]~145 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.437 ns Q2\[6\]~147 8 COMB LCCOMB_X21_Y12_N16 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 1.437 ns; Loc. = LCCOMB_X21_Y12_N16; Fanout = 2; COMB Node = 'Q2\[6\]~147'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[5]~145 Q2[6]~147 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.517 ns Q2\[7\]~149 9 COMB LCCOMB_X21_Y12_N18 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 1.517 ns; Loc. = LCCOMB_X21_Y12_N18; Fanout = 2; COMB Node = 'Q2\[7\]~149'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[6]~147 Q2[7]~149 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.597 ns Q2\[8\]~151 10 COMB LCCOMB_X21_Y12_N20 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 1.597 ns; Loc. = LCCOMB_X21_Y12_N20; Fanout = 2; COMB Node = 'Q2\[8\]~151'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[7]~149 Q2[8]~151 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.677 ns Q2\[9\]~153 11 COMB LCCOMB_X21_Y12_N22 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 1.677 ns; Loc. = LCCOMB_X21_Y12_N22; Fanout = 2; COMB Node = 'Q2\[9\]~153'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[8]~151 Q2[9]~153 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.757 ns Q2\[10\]~155 12 COMB LCCOMB_X21_Y12_N24 1 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 1.757 ns; Loc. = LCCOMB_X21_Y12_N24; Fanout = 1; COMB Node = 'Q2\[10\]~155'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q2[9]~153 Q2[10]~155 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 2.215 ns Q2\[11\]~156 13 COMB LCCOMB_X21_Y12_N26 1 " "Info: 13: + IC(0.000 ns) + CELL(0.458 ns) = 2.215 ns; Loc. = LCCOMB_X21_Y12_N26; Fanout = 1; COMB Node = 'Q2\[11\]~156'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Q2[10]~155 Q2[11]~156 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.311 ns Q2\[11\] 14 REG LCFF_X21_Y12_N27 2 " "Info: 14: + IC(0.000 ns) + CELL(0.096 ns) = 2.311 ns; Loc. = LCFF_X21_Y12_N27; Fanout = 2; REG Node = 'Q2\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Q2[11]~156 Q2[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.943 ns ( 84.08 % ) " "Info: Total cell delay = 1.943 ns ( 84.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.368 ns ( 15.92 % ) " "Info: Total interconnect delay = 0.368 ns ( 15.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.311 ns" { Q2[0] Q2[0]~135 Q2[1]~137 Q2[2]~139 Q2[3]~141 Q2[4]~143 Q2[5]~145 Q2[6]~147 Q2[7]~149 Q2[8]~151 Q2[9]~153 Q2[10]~155 Q2[11]~156 Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.311 ns" { Q2[0] {} Q2[0]~135 {} Q2[1]~137 {} Q2[2]~139 {} Q2[3]~141 {} Q2[4]~143 {} Q2[5]~145 {} Q2[6]~147 {} Q2[7]~149 {} Q2[8]~151 {} Q2[9]~153 {} Q2[10]~155 {} Q2[11]~156 {} Q2[11] {} } { 0.000ns 0.368ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.584 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.602 ns) 2.584 ns Q2\[11\] 3 REG LCFF_X21_Y12_N27 2 " "Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X21_Y12_N27; Fanout = 2; REG Node = 'Q2\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.386 ns" { clk~clkctrl Q2[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.55 % ) " "Info: Total cell delay = 1.668 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.916 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.916 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[11] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.584 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.602 ns) 2.584 ns Q2\[0\] 3 REG LCFF_X21_Y12_N5 3 " "Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X21_Y12_N5; Fanout = 3; REG Node = 'Q2\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.386 ns" { clk~clkctrl Q2[0] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.55 % ) " "Info: Total cell delay = 1.668 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.916 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.916 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[0] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[11] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[0] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.311 ns" { Q2[0] Q2[0]~135 Q2[1]~137 Q2[2]~139 Q2[3]~141 Q2[4]~143 Q2[5]~145 Q2[6]~147 Q2[7]~149 Q2[8]~151 Q2[9]~153 Q2[10]~155 Q2[11]~156 Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.311 ns" { Q2[0] {} Q2[0]~135 {} Q2[1]~137 {} Q2[2]~139 {} Q2[3]~141 {} Q2[4]~143 {} Q2[5]~145 {} Q2[6]~147 {} Q2[7]~149 {} Q2[8]~151 {} Q2[9]~153 {} Q2[10]~155 {} Q2[11]~156 {} Q2[11] {} } { 0.000ns 0.368ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[11] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[0] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { Q2[11] {} } {  } {  } "" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "DCLK1 register register X1\[0\] M1~reg0 380.08 MHz Internal " "Info: Clock \"DCLK1\" Internal fmax is restricted to 380.08 MHz between source register \"X1\[0\]\" and destination register \"M1~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.119 ns + Longest register register " "Info: + Longest register to register delay is 2.119 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns X1\[0\] 1 REG LCFF_X18_Y6_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y6_N7; Fanout = 1; REG Node = 'X1\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { X1[0] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.379 ns) + CELL(0.545 ns) 0.924 ns LessThan0~288 2 COMB LCCOMB_X18_Y6_N0 1 " "Info: 2: + IC(0.379 ns) + CELL(0.545 ns) = 0.924 ns; Loc. = LCCOMB_X18_Y6_N0; Fanout = 1; COMB Node = 'LessThan0~288'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.924 ns" { X1[0] LessThan0~288 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1630 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.286 ns) + CELL(0.178 ns) 1.388 ns LessThan0~289 3 COMB LCCOMB_X18_Y6_N14 1 " "Info: 3: + IC(0.286 ns) + CELL(0.178 ns) = 1.388 ns; Loc. = LCCOMB_X18_Y6_N14; Fanout = 1; COMB Node = 'LessThan0~289'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.464 ns" { LessThan0~288 LessThan0~289 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1630 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.457 ns) + CELL(0.178 ns) 2.023 ns LessThan0~290 4 COMB LCCOMB_X19_Y6_N6 1 " "Info: 4: + IC(0.457 ns) + CELL(0.178 ns) = 2.023 ns; Loc. = LCCOMB_X19_Y6_N6; Fanout = 1; COMB Node = 'LessThan0~290'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.635 ns" { LessThan0~289 LessThan0~290 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1630 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.119 ns M1~reg0 5 REG LCFF_X19_Y6_N7 1 " "Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 2.119 ns; Loc. = LCFF_X19_Y6_N7; Fanout = 1; REG Node = 'M1~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LessThan0~290 M1~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.997 ns ( 47.05 % ) " "Info: Total cell delay = 0.997 ns ( 47.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.122 ns ( 52.95 % ) " "Info: Total interconnect delay = 1.122 ns ( 52.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.119 ns" { X1[0] LessThan0~288 LessThan0~289 LessThan0~290 M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.119 ns" { X1[0] {} LessThan0~288 {} LessThan0~289 {} LessThan0~290 {} M1~reg0 {} } { 0.000ns 0.379ns 0.286ns 0.457ns 0.000ns } { 0.000ns 0.545ns 0.178ns 0.178ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK1 destination 2.542 ns + Shortest register " "Info: + Shortest clock path from clock \"DCLK1\" to destination register is 2.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns DCLK1 1 CLK PIN_24 13 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK1 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.188 ns DCLK1~clkctrl 2 COMB CLKCTRL_G1 13 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'DCLK1~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK1 DCLK1~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.602 ns) 2.542 ns M1~reg0 3 REG LCFF_X19_Y6_N7 1 " "Info: 3: + IC(0.752 ns) + CELL(0.602 ns) = 2.542 ns; Loc. = LCFF_X19_Y6_N7; Fanout = 1; REG Node = 'M1~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.354 ns" { DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 65.22 % ) " "Info: Total cell delay = 1.658 ns ( 65.22 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.884 ns ( 34.78 % ) " "Info: Total interconnect delay = 0.884 ns ( 34.78 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.542 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.752ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK1 source 2.540 ns - Longest register " "Info: - Longest clock path from clock \"DCLK1\" to source register is 2.540 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns DCLK1 1 CLK PIN_24 13 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK1 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.188 ns DCLK1~clkctrl 2 COMB CLKCTRL_G1 13 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'DCLK1~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK1 DCLK1~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.602 ns) 2.540 ns X1\[0\] 3 REG LCFF_X18_Y6_N7 1 " "Info: 3: + IC(0.750 ns) + CELL(0.602 ns) = 2.540 ns; Loc. = LCFF_X18_Y6_N7; Fanout = 1; REG Node = 'X1\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.352 ns" { DCLK1~clkctrl X1[0] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 65.28 % ) " "Info: Total cell delay = 1.658 ns ( 65.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.882 ns ( 34.72 % ) " "Info: Total interconnect delay = 0.882 ns ( 34.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { DCLK1 DCLK1~clkctrl X1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.540 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} X1[0] {} } { 0.000ns 0.000ns 0.132ns 0.750ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.542 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.752ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { DCLK1 DCLK1~clkctrl X1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.540 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} X1[0] {} } { 0.000ns 0.000ns 0.132ns 0.750ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.119 ns" { X1[0] LessThan0~288 LessThan0~289 LessThan0~290 M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.119 ns" { X1[0] {} LessThan0~288 {} LessThan0~289 {} LessThan0~290 {} M1~reg0 {} } { 0.000ns 0.379ns 0.286ns 0.457ns 0.000ns } { 0.000ns 0.545ns 0.178ns 0.178ns 0.096ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.542 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.752ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { DCLK1 DCLK1~clkctrl X1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.540 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} X1[0] {} } { 0.000ns 0.000ns 0.132ns 0.750ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { M1~reg0 {} } {  } {  } "" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}