lianglu.tan.qmsg

该程序可是多路频率检测

{ "Info" "ITDB_FULL_TCO_RESULT" "DCLK1 M1 M1~reg0 7.455 ns register " "Info: tco from clock \"DCLK1\" to destination pin \"M1\" through register \"M1~reg0\" is 7.455 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK1 source 2.573 ns + Longest register " "Info: + Longest clock path from clock \"DCLK1\" to source register is 2.573 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns DCLK1 1 CLK PIN_24 13 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK1 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.188 ns DCLK1~clkctrl 2 COMB CLKCTRL_G1 10 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'DCLK1~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK1 DCLK1~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.602 ns) 2.573 ns M1~reg0 3 REG LCFF_X22_Y11_N7 1 " "Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.573 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 64.44 % ) " "Info: Total cell delay = 1.658 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.915 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.915 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.605 ns + Longest register pin " "Info: + Longest register to pin delay is 4.605 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns M1~reg0 1 REG LCFF_X22_Y11_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { M1~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.549 ns) + CELL(3.056 ns) 4.605 ns M1 2 PIN PIN_187 0 " "Info: 2: + IC(1.549 ns) + CELL(3.056 ns) = 4.605 ns; Loc. = PIN_187; Fanout = 0; PIN Node = 'M1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.605 ns" { M1~reg0 M1 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.056 ns ( 66.36 % ) " "Info: Total cell delay = 3.056 ns ( 66.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.549 ns ( 33.64 % ) " "Info: Total interconnect delay = 1.549 ns ( 33.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.605 ns" { M1~reg0 M1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.605 ns" { M1~reg0 {} M1 {} } { 0.000ns 1.549ns } { 0.000ns 3.056ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.605 ns" { M1~reg0 M1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.605 ns" { M1~reg0 {} M1 {} } { 0.000ns 1.549ns } { 0.000ns 3.056ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "Q1\[11\] DCLK1 clk -0.398 ns register " "Info: th for register \"Q1\[11\]\" (data pin = \"DCLK1\", clock pin = \"clk\") is -0.398 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.583 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.602 ns) 2.583 ns Q1\[11\] 3 REG LCFF_X22_Y11_N31 2 " "Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.583 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'Q1\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { clk~clkctrl Q1[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.58 % ) " "Info: Total cell delay = 1.668 ns ( 64.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.915 ns ( 35.42 % ) " "Info: Total interconnect delay = 0.915 ns ( 35.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.583 ns" { clk clk~clkctrl Q1[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.583 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[11] {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.267 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns DCLK1 1 CLK PIN_24 13 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK1 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.580 ns) 3.267 ns Q1\[11\] 2 REG LCFF_X22_Y11_N31 2 " "Info: 2: + IC(1.631 ns) + CELL(0.580 ns) = 3.267 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'Q1\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.211 ns" { DCLK1 Q1[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.636 ns ( 50.08 % ) " "Info: Total cell delay = 1.636 ns ( 50.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.631 ns ( 49.92 % ) " "Info: Total interconnect delay = 1.631 ns ( 49.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin