lianglu.tan.qmsg

该程序可是多路频率检测

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "DCLK2 register register X2\[10\] M2~reg0 380.08 MHz Internal " "Info: Clock \"DCLK2\" Internal fmax is restricted to 380.08 MHz between source register \"X2\[10\]\" and destination register \"M2~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.751 ns + Longest register register " "Info: + Longest register to register delay is 1.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns X2\[10\] 1 REG LCFF_X25_Y11_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y11_N3; Fanout = 1; REG Node = 'X2\[10\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { X2[10] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.355 ns) + CELL(0.458 ns) 0.813 ns LessThan1~159 2 COMB LCCOMB_X25_Y11_N16 1 " "Info: 2: + IC(0.355 ns) + CELL(0.458 ns) = 0.813 ns; Loc. = LCCOMB_X25_Y11_N16; Fanout = 1; COMB Node = 'LessThan1~159'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.813 ns" { X2[10] LessThan1~159 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1482 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.319 ns) 1.655 ns LessThan1~161 3 COMB LCCOMB_X25_Y10_N28 1 " "Info: 3: + IC(0.523 ns) + CELL(0.319 ns) = 1.655 ns; Loc. = LCCOMB_X25_Y10_N28; Fanout = 1; COMB Node = 'LessThan1~161'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.842 ns" { LessThan1~159 LessThan1~161 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1482 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 1.751 ns M2~reg0 4 REG LCFF_X25_Y10_N29 1 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 1.751 ns; Loc. = LCFF_X25_Y10_N29; Fanout = 1; REG Node = 'M2~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LessThan1~161 M2~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.873 ns ( 49.86 % ) " "Info: Total cell delay = 0.873 ns ( 49.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.878 ns ( 50.14 % ) " "Info: Total interconnect delay = 0.878 ns ( 50.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { X2[10] LessThan1~159 LessThan1~161 M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.751 ns" { X2[10] {} LessThan1~159 {} LessThan1~161 {} M2~reg0 {} } { 0.000ns 0.355ns 0.523ns 0.000ns } { 0.000ns 0.458ns 0.319ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.004 ns - Smallest " "Info: - Smallest clock skew is -0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK2 destination 2.584 ns + Shortest register " "Info: + Shortest clock path from clock \"DCLK2\" to destination register is 2.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns DCLK2 1 CLK PIN_27 13 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_27; Fanout = 13; CLK Node = 'DCLK2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK2 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns DCLK2~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'DCLK2~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK2 DCLK2~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.602 ns) 2.584 ns M2~reg0 3 REG LCFF_X25_Y10_N29 1 " "Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X25_Y10_N29; Fanout = 1; REG Node = 'M2~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.386 ns" { DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.55 % ) " "Info: Total cell delay = 1.668 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.916 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.916 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} M2~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK2 source 2.588 ns - Longest register " "Info: - Longest clock path from clock \"DCLK2\" to source register is 2.588 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns DCLK2 1 CLK PIN_27 13 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_27; Fanout = 13; CLK Node = 'DCLK2'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK2 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns DCLK2~clkctrl 2 COMB CLKCTRL_G3 10 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'DCLK2~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK2 DCLK2~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.788 ns) + CELL(0.602 ns) 2.588 ns X2\[10\] 3 REG LCFF_X25_Y11_N3 1 " "Info: 3: + IC(0.788 ns) + CELL(0.602 ns) = 2.588 ns; Loc. = LCFF_X25_Y11_N3; Fanout = 1; REG Node = 'X2\[10\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.390 ns" { DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.45 % ) " "Info: Total cell delay = 1.668 ns ( 64.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.920 ns ( 35.55 % ) " "Info: Total interconnect delay = 0.920 ns ( 35.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.588 ns" { DCLK2 DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.588 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} X2[10] {} } { 0.000ns 0.000ns 0.132ns 0.788ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} M2~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.588 ns" { DCLK2 DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.588 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} X2[10] {} } { 0.000ns 0.000ns 0.132ns 0.788ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.751 ns" { X2[10] LessThan1~159 LessThan1~161 M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.751 ns" { X2[10] {} LessThan1~159 {} LessThan1~161 {} M2~reg0 {} } { 0.000ns 0.355ns 0.523ns 0.000ns } { 0.000ns 0.458ns 0.319ns 0.096ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { DCLK2 DCLK2~clkctrl M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} M2~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.588 ns" { DCLK2 DCLK2~clkctrl X2[10] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.588 ns" { DCLK2 {} DCLK2~combout {} DCLK2~clkctrl {} X2[10] {} } { 0.000ns 0.000ns 0.132ns 0.788ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { M2~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { M2~reg0 {} } {  } {  } "" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 55 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "Q2\[11\] ENA clk 5.089 ns register " "Info: tsu for register \"Q2\[11\]\" (data pin = \"ENA\", clock pin = \"clk\") is 5.089 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.711 ns + Longest pin register " "Info: + Longest pin to register delay is 7.711 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.893 ns) 0.893 ns ENA 1 PIN PIN_185 24 " "Info: 1: + IC(0.000 ns) + CELL(0.893 ns) = 0.893 ns; Loc. = PIN_185; Fanout = 24; PIN Node = 'ENA'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { ENA } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.060 ns) + CELL(0.758 ns) 7.711 ns Q2\[11\] 2 REG LCFF_X25_Y10_N27 2 " "Info: 2: + IC(6.060 ns) + CELL(0.758 ns) = 7.711 ns; Loc. = LCFF_X25_Y10_N27; Fanout = 2; REG Node = 'Q2\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.818 ns" { ENA Q2[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.651 ns ( 21.41 % ) " "Info: Total cell delay = 1.651 ns ( 21.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.060 ns ( 78.59 % ) " "Info: Total interconnect delay = 6.060 ns ( 78.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.711 ns" { ENA Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.711 ns" { ENA {} ENA~combout {} Q2[11] {} } { 0.000ns 0.000ns 6.060ns } { 0.000ns 0.893ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.584 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.784 ns) + CELL(0.602 ns) 2.584 ns Q2\[11\] 3 REG LCFF_X25_Y10_N27 2 " "Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X25_Y10_N27; Fanout = 2; REG Node = 'Q2\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.386 ns" { clk~clkctrl Q2[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.55 % ) " "Info: Total cell delay = 1.668 ns ( 64.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.916 ns ( 35.45 % ) " "Info: Total interconnect delay = 0.916 ns ( 35.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[11] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.711 ns" { ENA Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.711 ns" { ENA {} ENA~combout {} Q2[11] {} } { 0.000ns 0.000ns 6.060ns } { 0.000ns 0.893ns 0.758ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.584 ns" { clk clk~clkctrl Q2[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.584 ns" { clk {} clk~combout {} clk~clkctrl {} Q2[11] {} } { 0.000ns 0.000ns 0.132ns 0.784ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}