lianglu.tan.qmsg

该程序可是多路频率检测

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register Q1\[0\] Q1\[11\] 380.08 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 380.08 MHz between source register \"Q1\[0\]\" and destination register \"Q1\[11\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.304 ns + Longest register register " "Info: + Longest register to register delay is 2.304 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Q1\[0\] 1 REG LCFF_X22_Y11_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y11_N9; Fanout = 2; REG Node = 'Q1\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q1[0] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.495 ns) 0.856 ns Q1\[0\]~791 2 COMB LCCOMB_X22_Y11_N8 2 " "Info: 2: + IC(0.361 ns) + CELL(0.495 ns) = 0.856 ns; Loc. = LCCOMB_X22_Y11_N8; Fanout = 2; COMB Node = 'Q1\[0\]~791'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.856 ns" { Q1[0] Q1[0]~791 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 0.936 ns Q1\[1\]~793 3 COMB LCCOMB_X22_Y11_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 0.936 ns; Loc. = LCCOMB_X22_Y11_N10; Fanout = 2; COMB Node = 'Q1\[1\]~793'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[0]~791 Q1[1]~793 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.016 ns Q1\[2\]~795 4 COMB LCCOMB_X22_Y11_N12 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.016 ns; Loc. = LCCOMB_X22_Y11_N12; Fanout = 2; COMB Node = 'Q1\[2\]~795'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[1]~793 Q1[2]~795 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.174 ns) 1.190 ns Q1\[3\]~797 5 COMB LCCOMB_X22_Y11_N14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.174 ns) = 1.190 ns; Loc. = LCCOMB_X22_Y11_N14; Fanout = 2; COMB Node = 'Q1\[3\]~797'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.174 ns" { Q1[2]~795 Q1[3]~797 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.270 ns Q1\[4\]~799 6 COMB LCCOMB_X22_Y11_N16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 1.270 ns; Loc. = LCCOMB_X22_Y11_N16; Fanout = 2; COMB Node = 'Q1\[4\]~799'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[3]~797 Q1[4]~799 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.350 ns Q1\[5\]~801 7 COMB LCCOMB_X22_Y11_N18 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 1.350 ns; Loc. = LCCOMB_X22_Y11_N18; Fanout = 2; COMB Node = 'Q1\[5\]~801'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[4]~799 Q1[5]~801 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.430 ns Q1\[6\]~803 8 COMB LCCOMB_X22_Y11_N20 2 " "Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 1.430 ns; Loc. = LCCOMB_X22_Y11_N20; Fanout = 2; COMB Node = 'Q1\[6\]~803'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[5]~801 Q1[6]~803 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.510 ns Q1\[7\]~805 9 COMB LCCOMB_X22_Y11_N22 2 " "Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 1.510 ns; Loc. = LCCOMB_X22_Y11_N22; Fanout = 2; COMB Node = 'Q1\[7\]~805'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[6]~803 Q1[7]~805 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.590 ns Q1\[8\]~807 10 COMB LCCOMB_X22_Y11_N24 2 " "Info: 10: + IC(0.000 ns) + CELL(0.080 ns) = 1.590 ns; Loc. = LCCOMB_X22_Y11_N24; Fanout = 2; COMB Node = 'Q1\[8\]~807'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[7]~805 Q1[8]~807 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.670 ns Q1\[9\]~809 11 COMB LCCOMB_X22_Y11_N26 2 " "Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 1.670 ns; Loc. = LCCOMB_X22_Y11_N26; Fanout = 2; COMB Node = 'Q1\[9\]~809'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[8]~807 Q1[9]~809 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.750 ns Q1\[10\]~811 12 COMB LCCOMB_X22_Y11_N28 1 " "Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 1.750 ns; Loc. = LCCOMB_X22_Y11_N28; Fanout = 1; COMB Node = 'Q1\[10\]~811'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.080 ns" { Q1[9]~809 Q1[10]~811 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.458 ns) 2.208 ns Q1\[11\]~812 13 COMB LCCOMB_X22_Y11_N30 1 " "Info: 13: + IC(0.000 ns) + CELL(0.458 ns) = 2.208 ns; Loc. = LCCOMB_X22_Y11_N30; Fanout = 1; COMB Node = 'Q1\[11\]~812'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { Q1[10]~811 Q1[11]~812 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.304 ns Q1\[11\] 14 REG LCFF_X22_Y11_N31 2 " "Info: 14: + IC(0.000 ns) + CELL(0.096 ns) = 2.304 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'Q1\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { Q1[11]~812 Q1[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.943 ns ( 84.33 % ) " "Info: Total cell delay = 1.943 ns ( 84.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.361 ns ( 15.67 % ) " "Info: Total interconnect delay = 0.361 ns ( 15.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.304 ns" { Q1[0] Q1[0]~791 Q1[1]~793 Q1[2]~795 Q1[3]~797 Q1[4]~799 Q1[5]~801 Q1[6]~803 Q1[7]~805 Q1[8]~807 Q1[9]~809 Q1[10]~811 Q1[11]~812 Q1[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.304 ns" { Q1[0] {} Q1[0]~791 {} Q1[1]~793 {} Q1[2]~795 {} Q1[3]~797 {} Q1[4]~799 {} Q1[5]~801 {} Q1[6]~803 {} Q1[7]~805 {} Q1[8]~807 {} Q1[9]~809 {} Q1[10]~811 {} Q1[11]~812 {} Q1[11] {} } { 0.000ns 0.361ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.583 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.602 ns) 2.583 ns Q1\[11\] 3 REG LCFF_X22_Y11_N31 2 " "Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.583 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'Q1\[11\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { clk~clkctrl Q1[11] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.58 % ) " "Info: Total cell delay = 1.668 ns ( 64.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.915 ns ( 35.42 % ) " "Info: Total interconnect delay = 0.915 ns ( 35.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.583 ns" { clk clk~clkctrl Q1[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.583 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[11] {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.583 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.066 ns) 1.066 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.198 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { clk clk~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.602 ns) 2.583 ns Q1\[0\] 3 REG LCFF_X22_Y11_N9 2 " "Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.583 ns; Loc. = LCFF_X22_Y11_N9; Fanout = 2; REG Node = 'Q1\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { clk~clkctrl Q1[0] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.668 ns ( 64.58 % ) " "Info: Total cell delay = 1.668 ns ( 64.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.915 ns ( 35.42 % ) " "Info: Total interconnect delay = 0.915 ns ( 35.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.583 ns" { clk clk~clkctrl Q1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.583 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[0] {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.583 ns" { clk clk~clkctrl Q1[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.583 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[11] {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.583 ns" { clk clk~clkctrl Q1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.583 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[0] {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.304 ns" { Q1[0] Q1[0]~791 Q1[1]~793 Q1[2]~795 Q1[3]~797 Q1[4]~799 Q1[5]~801 Q1[6]~803 Q1[7]~805 Q1[8]~807 Q1[9]~809 Q1[10]~811 Q1[11]~812 Q1[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.304 ns" { Q1[0] {} Q1[0]~791 {} Q1[1]~793 {} Q1[2]~795 {} Q1[3]~797 {} Q1[4]~799 {} Q1[5]~801 {} Q1[6]~803 {} Q1[7]~805 {} Q1[8]~807 {} Q1[9]~809 {} Q1[10]~811 {} Q1[11]~812 {} Q1[11] {} } { 0.000ns 0.361ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.495ns 0.080ns 0.080ns 0.174ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.080ns 0.458ns 0.096ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.583 ns" { clk clk~clkctrl Q1[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.583 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[11] {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.583 ns" { clk clk~clkctrl Q1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.583 ns" { clk {} clk~combout {} clk~clkctrl {} Q1[0] {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.066ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { Q1[11] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { Q1[11] {} } {  } {  } "" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 20 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "DCLK1 register register X1\[4\] M1~reg0 380.08 MHz Internal " "Info: Clock \"DCLK1\" Internal fmax is restricted to 380.08 MHz between source register \"X1\[4\]\" and destination register \"M1~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.631 ns " "Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.034 ns + Longest register register " "Info: + Longest register to register delay is 2.034 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns X1\[4\] 1 REG LCFF_X21_Y11_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y11_N7; Fanout = 1; REG Node = 'X1\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { X1[4] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.545 ns) 0.916 ns LessThan0~160 2 COMB LCCOMB_X21_Y11_N14 1 " "Info: 2: + IC(0.371 ns) + CELL(0.545 ns) = 0.916 ns; Loc. = LCCOMB_X21_Y11_N14; Fanout = 1; COMB Node = 'LessThan0~160'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.916 ns" { X1[4] LessThan0~160 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1482 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.544 ns) 1.938 ns LessThan0~161 3 COMB LCCOMB_X22_Y11_N6 1 " "Info: 3: + IC(0.478 ns) + CELL(0.544 ns) = 1.938 ns; Loc. = LCCOMB_X22_Y11_N6; Fanout = 1; COMB Node = 'LessThan0~161'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.022 ns" { LessThan0~160 LessThan0~161 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1482 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.034 ns M1~reg0 4 REG LCFF_X22_Y11_N7 1 " "Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 2.034 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { LessThan0~161 M1~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.185 ns ( 58.26 % ) " "Info: Total cell delay = 1.185 ns ( 58.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.849 ns ( 41.74 % ) " "Info: Total interconnect delay = 0.849 ns ( 41.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.034 ns" { X1[4] LessThan0~160 LessThan0~161 M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.034 ns" { X1[4] {} LessThan0~160 {} LessThan0~161 {} M1~reg0 {} } { 0.000ns 0.371ns 0.478ns 0.000ns } { 0.000ns 0.545ns 0.544ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK1 destination 2.573 ns + Shortest register " "Info: + Shortest clock path from clock \"DCLK1\" to destination register is 2.573 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns DCLK1 1 CLK PIN_24 13 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK1 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.188 ns DCLK1~clkctrl 2 COMB CLKCTRL_G1 10 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'DCLK1~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK1 DCLK1~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.602 ns) 2.573 ns M1~reg0 3 REG LCFF_X22_Y11_N7 1 " "Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.573 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.385 ns" { DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 64.44 % ) " "Info: Total cell delay = 1.658 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.915 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.915 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "DCLK1 source 2.572 ns - Longest register " "Info: - Longest clock path from clock \"DCLK1\" to source register is 2.572 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.056 ns) 1.056 ns DCLK1 1 CLK PIN_24 13 " "Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { DCLK1 } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.132 ns) + CELL(0.000 ns) 1.188 ns DCLK1~clkctrl 2 COMB CLKCTRL_G1 10 " "Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'DCLK1~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.132 ns" { DCLK1 DCLK1~clkctrl } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.782 ns) + CELL(0.602 ns) 2.572 ns X1\[4\] 3 REG LCFF_X21_Y11_N7 1 " "Info: 3: + IC(0.782 ns) + CELL(0.602 ns) = 2.572 ns; Loc. = LCFF_X21_Y11_N7; Fanout = 1; REG Node = 'X1\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.384 ns" { DCLK1~clkctrl X1[4] } "NODE_NAME" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.658 ns ( 64.46 % ) " "Info: Total cell delay = 1.658 ns ( 64.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.914 ns ( 35.54 % ) " "Info: Total interconnect delay = 0.914 ns ( 35.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.572 ns" { DCLK1 DCLK1~clkctrl X1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.572 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} X1[4] {} } { 0.000ns 0.000ns 0.132ns 0.782ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.572 ns" { DCLK1 DCLK1~clkctrl X1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.572 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} X1[4] {} } { 0.000ns 0.000ns 0.132ns 0.782ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.034 ns" { X1[4] LessThan0~160 LessThan0~161 M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.034 ns" { X1[4] {} LessThan0~160 {} LessThan0~161 {} M1~reg0 {} } { 0.000ns 0.371ns 0.478ns 0.000ns } { 0.000ns 0.545ns 0.544ns 0.096ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.573 ns" { DCLK1 DCLK1~clkctrl M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.573 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} M1~reg0 {} } { 0.000ns 0.000ns 0.132ns 0.783ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.572 ns" { DCLK1 DCLK1~clkctrl X1[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.572 ns" { DCLK1 {} DCLK1~combout {} DCLK1~clkctrl {} X1[4] {} } { 0.000ns 0.000ns 0.132ns 0.782ns } { 0.000ns 1.056ns 0.000ns 0.602ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { M1~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { M1~reg0 {} } {  } {  } "" } } { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 46 0 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}