lianglu.tan.qmsg

该程序可是多路频率检测

{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off lianglu -c lianglu --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off lianglu -c lianglu --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 6 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "DCLK1 " "Info: Assuming node \"DCLK1\" is an undefined clock" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DCLK1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "DCLK2 " "Info: Assuming node \"DCLK2\" is an undefined clock" {  } { { "lianglu.vhd" "" { Text "D:/CPLD开发训练/863Lianglujiance/lianglu.vhd" 7 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "DCLK2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}