lianglu.sim.rpt

该程序可是多路频率检测

; |lianglu|Q2[6]~146     ; |lianglu|Q2[6]~146     ; combout          ;
; |lianglu|Q2[6]~146     ; |lianglu|Q2[6]~147     ; cout             ;
; |lianglu|Q2[7]~148     ; |lianglu|Q2[7]~148     ; combout          ;
; |lianglu|Q2[7]~148     ; |lianglu|Q2[7]~149     ; cout             ;
; |lianglu|Q2[8]~150     ; |lianglu|Q2[8]~150     ; combout          ;
; |lianglu|Q2[8]~150     ; |lianglu|Q2[8]~151     ; cout             ;
; |lianglu|Q2[9]~152     ; |lianglu|Q2[9]~152     ; combout          ;
; |lianglu|M1~reg0       ; |lianglu|M1~reg0       ; regout           ;
; |lianglu|M2~reg0       ; |lianglu|M2~reg0       ; regout           ;
; |lianglu|M1            ; |lianglu|M1            ; padio            ;
; |lianglu|M2            ; |lianglu|M2            ; padio            ;
; |lianglu|DCLK1         ; |lianglu|DCLK1~corein  ; combout          ;
; |lianglu|DCLK2         ; |lianglu|DCLK2~corein  ; combout          ;
; |lianglu|clk           ; |lianglu|clk~corein    ; combout          ;
; |lianglu|DCLK1~clkctrl ; |lianglu|DCLK1~clkctrl ; outclk           ;
; |lianglu|DCLK2~clkctrl ; |lianglu|DCLK2~clkctrl ; outclk           ;
; |lianglu|clk~clkctrl   ; |lianglu|clk~clkctrl   ; outclk           ;
; |lianglu|X1[7]~feeder  ; |lianglu|X1[7]~feeder  ; combout          ;
; |lianglu|X1[6]~feeder  ; |lianglu|X1[6]~feeder  ; combout          ;
; |lianglu|X2[4]~feeder  ; |lianglu|X2[4]~feeder  ; combout          ;
; |lianglu|X2[3]~feeder  ; |lianglu|X2[3]~feeder  ; combout          ;
; |lianglu|X2[7]~feeder  ; |lianglu|X2[7]~feeder  ; combout          ;
; |lianglu|X2[6]~feeder  ; |lianglu|X2[6]~feeder  ; combout          ;
+------------------------+------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------+
; Missing 1-Value Coverage                                           ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |lianglu|Q1[11]        ; |lianglu|Q1[11]        ; regout           ;
; |lianglu|Q1[10]        ; |lianglu|Q1[10]        ; regout           ;
; |lianglu|Q1[9]         ; |lianglu|Q1[9]         ; regout           ;
; |lianglu|Q1[8]         ; |lianglu|Q1[8]         ; regout           ;
; |lianglu|Q2[11]        ; |lianglu|Q2[11]        ; regout           ;
; |lianglu|Q2[10]        ; |lianglu|Q2[10]        ; regout           ;
; |lianglu|Q2[9]         ; |lianglu|Q2[9]         ; regout           ;
; |lianglu|Q1[8]~806     ; |lianglu|Q1[8]~807     ; cout             ;
; |lianglu|Q1[9]~808     ; |lianglu|Q1[9]~808     ; combout          ;
; |lianglu|Q1[9]~808     ; |lianglu|Q1[9]~809     ; cout             ;
; |lianglu|Q1[10]~810    ; |lianglu|Q1[10]~810    ; combout          ;
; |lianglu|Q1[10]~810    ; |lianglu|Q1[10]~811    ; cout             ;
; |lianglu|Q1[11]~812    ; |lianglu|Q1[11]~812    ; combout          ;
; |lianglu|Q2[9]~152     ; |lianglu|Q2[9]~153     ; cout             ;
; |lianglu|Q2[10]~154    ; |lianglu|Q2[10]~154    ; combout          ;
; |lianglu|Q2[10]~154    ; |lianglu|Q2[10]~155    ; cout             ;
; |lianglu|Q2[11]~156    ; |lianglu|Q2[11]~156    ; combout          ;
; |lianglu|X1[11]        ; |lianglu|X1[11]        ; regout           ;
; |lianglu|X1[10]        ; |lianglu|X1[10]        ; regout           ;
; |lianglu|X1[9]         ; |lianglu|X1[9]         ; regout           ;
; |lianglu|X1[8]         ; |lianglu|X1[8]         ; regout           ;
; |lianglu|LessThan0~159 ; |lianglu|LessThan0~159 ; combout          ;
; |lianglu|X1[5]         ; |lianglu|X1[5]         ; regout           ;
; |lianglu|X1[4]         ; |lianglu|X1[4]         ; regout           ;
; |lianglu|LessThan0~160 ; |lianglu|LessThan0~160 ; combout          ;
; |lianglu|LessThan0~161 ; |lianglu|LessThan0~161 ; combout          ;
; |lianglu|X2[11]        ; |lianglu|X2[11]        ; regout           ;
; |lianglu|X2[10]        ; |lianglu|X2[10]        ; regout           ;
; |lianglu|X2[9]         ; |lianglu|X2[9]         ; regout           ;
; |lianglu|LessThan1~159 ; |lianglu|LessThan1~159 ; combout          ;
; |lianglu|X2[3]         ; |lianglu|X2[3]         ; regout           ;
; |lianglu|LessThan1~160 ; |lianglu|LessThan1~160 ; combout          ;
; |lianglu|LessThan1~161 ; |lianglu|LessThan1~161 ; combout          ;
; |lianglu|Clr           ; |lianglu|Clr~corein    ; combout          ;
; |lianglu|ENA           ; |lianglu|ENA~corein    ; combout          ;
; |lianglu|Clr~clkctrl   ; |lianglu|Clr~clkctrl   ; outclk           ;
; |lianglu|X1[11]~feeder ; |lianglu|X1[11]~feeder ; combout          ;
; |lianglu|X1[10]~feeder ; |lianglu|X1[10]~feeder ; combout          ;
; |lianglu|X2[11]~feeder ; |lianglu|X2[11]~feeder ; combout          ;
; |lianglu|X2[10]~feeder ; |lianglu|X2[10]~feeder ; combout          ;
+------------------------+------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------+
; Missing 0-Value Coverage                                           ;
+------------------------+------------------------+------------------+
; Node Name              ; Output Port Name       ; Output Port Type ;
+------------------------+------------------------+------------------+
; |lianglu|Q1[11]        ; |lianglu|Q1[11]        ; regout           ;
; |lianglu|Q1[10]        ; |lianglu|Q1[10]        ; regout           ;
; |lianglu|Q1[9]         ; |lianglu|Q1[9]         ; regout           ;
; |lianglu|Q1[8]         ; |lianglu|Q1[8]         ; regout           ;
; |lianglu|Q2[11]        ; |lianglu|Q2[11]        ; regout           ;
; |lianglu|Q2[10]        ; |lianglu|Q2[10]        ; regout           ;
; |lianglu|Q2[9]         ; |lianglu|Q2[9]         ; regout           ;
; |lianglu|Q1[8]~806     ; |lianglu|Q1[8]~807     ; cout             ;
; |lianglu|Q1[9]~808     ; |lianglu|Q1[9]~808     ; combout          ;
; |lianglu|Q1[9]~808     ; |lianglu|Q1[9]~809     ; cout             ;
; |lianglu|Q1[10]~810    ; |lianglu|Q1[10]~810    ; combout          ;
; |lianglu|Q1[10]~810    ; |lianglu|Q1[10]~811    ; cout             ;
; |lianglu|Q1[11]~812    ; |lianglu|Q1[11]~812    ; combout          ;
; |lianglu|Q2[9]~152     ; |lianglu|Q2[9]~153     ; cout             ;
; |lianglu|Q2[10]~154    ; |lianglu|Q2[10]~154    ; combout          ;
; |lianglu|Q2[10]~154    ; |lianglu|Q2[10]~155    ; cout             ;
; |lianglu|Q2[11]~156    ; |lianglu|Q2[11]~156    ; combout          ;
; |lianglu|X1[11]        ; |lianglu|X1[11]        ; regout           ;
; |lianglu|X1[10]        ; |lianglu|X1[10]        ; regout           ;
; |lianglu|X1[9]         ; |lianglu|X1[9]         ; regout           ;
; |lianglu|X1[8]         ; |lianglu|X1[8]         ; regout           ;
; |lianglu|LessThan0~159 ; |lianglu|LessThan0~159 ; combout          ;
; |lianglu|X1[5]         ; |lianglu|X1[5]         ; regout           ;
; |lianglu|X1[4]         ; |lianglu|X1[4]         ; regout           ;
; |lianglu|X1[3]         ; |lianglu|X1[3]         ; regout           ;
; |lianglu|X1[7]         ; |lianglu|X1[7]         ; regout           ;
; |lianglu|X1[6]         ; |lianglu|X1[6]         ; regout           ;
; |lianglu|X2[11]        ; |lianglu|X2[11]        ; regout           ;
; |lianglu|X2[10]        ; |lianglu|X2[10]        ; regout           ;
; |lianglu|X2[9]         ; |lianglu|X2[9]         ; regout           ;
; |lianglu|X2[8]         ; |lianglu|X2[8]         ; regout           ;
; |lianglu|X2[5]         ; |lianglu|X2[5]         ; regout           ;
; |lianglu|X2[4]         ; |lianglu|X2[4]         ; regout           ;
; |lianglu|X2[3]         ; |lianglu|X2[3]         ; regout           ;
; |lianglu|X2[7]         ; |lianglu|X2[7]         ; regout           ;
; |lianglu|X2[6]         ; |lianglu|X2[6]         ; regout           ;
; |lianglu|Clr           ; |lianglu|Clr~corein    ; combout          ;
; |lianglu|ENA           ; |lianglu|ENA~corein    ; combout          ;
; |lianglu|Clr~clkctrl   ; |lianglu|Clr~clkctrl   ; outclk           ;
; |lianglu|X1[11]~feeder ; |lianglu|X1[11]~feeder ; combout          ;
; |lianglu|X1[10]~feeder ; |lianglu|X1[10]~feeder ; combout          ;
; |lianglu|X2[11]~feeder ; |lianglu|X2[11]~feeder ; combout          ;
; |lianglu|X2[10]~feeder ; |lianglu|X2[10]~feeder ; combout          ;
+------------------------+------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Mar 14 22:35:41 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off lianglu -c lianglu
Info: Using vector source file "D:/CPLD开发训练/863Lianglujiance/lianglu.vwf"
Warning: Ignored node in vector source file. Can't find corresponding node name "DCLK3" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "M3" in design.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      58.97 %
Info: Number of transitions in simulation is 274747
Info: Quartus II Simulator was successful. 0 errors, 2 warnings
    Info: Allocated 101 megabytes of memory during processing
    Info: Processing ended: Fri Mar 14 22:35:50 2008
    Info: Elapsed time: 00:00:09