lianglu.tan.rpt

该程序可是多路频率检测

            Info: Total cell delay = 1.943 ns ( 84.33 % )
            Info: Total interconnect delay = 0.361 ns ( 15.67 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.583 ns
                Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.583 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'Q1[11]'
                Info: Total cell delay = 1.668 ns ( 64.58 % )
                Info: Total interconnect delay = 0.915 ns ( 35.42 % )
            Info: - Longest clock path from clock "clk" to source register is 2.583 ns
                Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.583 ns; Loc. = LCFF_X22_Y11_N9; Fanout = 2; REG Node = 'Q1[0]'
                Info: Total cell delay = 1.668 ns ( 64.58 % )
                Info: Total interconnect delay = 0.915 ns ( 35.42 % )
        Info: + Micro clock to output delay of source is 0.277 ns
        Info: + Micro setup delay of destination is -0.038 ns
Info: Clock "DCLK1" Internal fmax is restricted to 380.08 MHz between source register "X1[4]" and destination register "M1~reg0"
    Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.034 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y11_N7; Fanout = 1; REG Node = 'X1[4]'
            Info: 2: + IC(0.371 ns) + CELL(0.545 ns) = 0.916 ns; Loc. = LCCOMB_X21_Y11_N14; Fanout = 1; COMB Node = 'LessThan0~160'
            Info: 3: + IC(0.478 ns) + CELL(0.544 ns) = 1.938 ns; Loc. = LCCOMB_X22_Y11_N6; Fanout = 1; COMB Node = 'LessThan0~161'
            Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 2.034 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'
            Info: Total cell delay = 1.185 ns ( 58.26 % )
            Info: Total interconnect delay = 0.849 ns ( 41.74 % )
        Info: - Smallest clock skew is 0.001 ns
            Info: + Shortest clock path from clock "DCLK1" to destination register is 2.573 ns
                Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'
                Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'DCLK1~clkctrl'
                Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.573 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'
                Info: Total cell delay = 1.658 ns ( 64.44 % )
                Info: Total interconnect delay = 0.915 ns ( 35.56 % )
            Info: - Longest clock path from clock "DCLK1" to source register is 2.572 ns
                Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'
                Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'DCLK1~clkctrl'
                Info: 3: + IC(0.782 ns) + CELL(0.602 ns) = 2.572 ns; Loc. = LCFF_X21_Y11_N7; Fanout = 1; REG Node = 'X1[4]'
                Info: Total cell delay = 1.658 ns ( 64.46 % )
                Info: Total interconnect delay = 0.914 ns ( 35.54 % )
        Info: + Micro clock to output delay of source is 0.277 ns
        Info: + Micro setup delay of destination is -0.038 ns
Info: Clock "DCLK2" Internal fmax is restricted to 380.08 MHz between source register "X2[10]" and destination register "M2~reg0"
    Info: fmax restricted to clock pin edge rate 2.631 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.751 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y11_N3; Fanout = 1; REG Node = 'X2[10]'
            Info: 2: + IC(0.355 ns) + CELL(0.458 ns) = 0.813 ns; Loc. = LCCOMB_X25_Y11_N16; Fanout = 1; COMB Node = 'LessThan1~159'
            Info: 3: + IC(0.523 ns) + CELL(0.319 ns) = 1.655 ns; Loc. = LCCOMB_X25_Y10_N28; Fanout = 1; COMB Node = 'LessThan1~161'
            Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 1.751 ns; Loc. = LCFF_X25_Y10_N29; Fanout = 1; REG Node = 'M2~reg0'
            Info: Total cell delay = 0.873 ns ( 49.86 % )
            Info: Total interconnect delay = 0.878 ns ( 50.14 % )
        Info: - Smallest clock skew is -0.004 ns
            Info: + Shortest clock path from clock "DCLK2" to destination register is 2.584 ns
                Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_27; Fanout = 13; CLK Node = 'DCLK2'
                Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'DCLK2~clkctrl'
                Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X25_Y10_N29; Fanout = 1; REG Node = 'M2~reg0'
                Info: Total cell delay = 1.668 ns ( 64.55 % )
                Info: Total interconnect delay = 0.916 ns ( 35.45 % )
            Info: - Longest clock path from clock "DCLK2" to source register is 2.588 ns
                Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_27; Fanout = 13; CLK Node = 'DCLK2'
                Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G3; Fanout = 10; COMB Node = 'DCLK2~clkctrl'
                Info: 3: + IC(0.788 ns) + CELL(0.602 ns) = 2.588 ns; Loc. = LCFF_X25_Y11_N3; Fanout = 1; REG Node = 'X2[10]'
                Info: Total cell delay = 1.668 ns ( 64.45 % )
                Info: Total interconnect delay = 0.920 ns ( 35.55 % )
        Info: + Micro clock to output delay of source is 0.277 ns
        Info: + Micro setup delay of destination is -0.038 ns
Info: tsu for register "Q2[11]" (data pin = "ENA", clock pin = "clk") is 5.089 ns
    Info: + Longest pin to register delay is 7.711 ns
        Info: 1: + IC(0.000 ns) + CELL(0.893 ns) = 0.893 ns; Loc. = PIN_185; Fanout = 24; PIN Node = 'ENA'
        Info: 2: + IC(6.060 ns) + CELL(0.758 ns) = 7.711 ns; Loc. = LCFF_X25_Y10_N27; Fanout = 2; REG Node = 'Q2[11]'
        Info: Total cell delay = 1.651 ns ( 21.41 % )
        Info: Total interconnect delay = 6.060 ns ( 78.59 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.584 ns
        Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.784 ns) + CELL(0.602 ns) = 2.584 ns; Loc. = LCFF_X25_Y10_N27; Fanout = 2; REG Node = 'Q2[11]'
        Info: Total cell delay = 1.668 ns ( 64.55 % )
        Info: Total interconnect delay = 0.916 ns ( 35.45 % )
Info: tco from clock "DCLK1" to destination pin "M1" through register "M1~reg0" is 7.455 ns
    Info: + Longest clock path from clock "DCLK1" to source register is 2.573 ns
        Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'
        Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.188 ns; Loc. = CLKCTRL_G1; Fanout = 10; COMB Node = 'DCLK1~clkctrl'
        Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.573 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'
        Info: Total cell delay = 1.658 ns ( 64.44 % )
        Info: Total interconnect delay = 0.915 ns ( 35.56 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 4.605 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y11_N7; Fanout = 1; REG Node = 'M1~reg0'
        Info: 2: + IC(1.549 ns) + CELL(3.056 ns) = 4.605 ns; Loc. = PIN_187; Fanout = 0; PIN Node = 'M1'
        Info: Total cell delay = 3.056 ns ( 66.36 % )
        Info: Total interconnect delay = 1.549 ns ( 33.64 % )
Info: th for register "Q1[11]" (data pin = "DCLK1", clock pin = "clk") is -0.398 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.583 ns
        Info: 1: + IC(0.000 ns) + CELL(1.066 ns) = 1.066 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.132 ns) + CELL(0.000 ns) = 1.198 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.783 ns) + CELL(0.602 ns) = 2.583 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'Q1[11]'
        Info: Total cell delay = 1.668 ns ( 64.58 % )
        Info: Total interconnect delay = 0.915 ns ( 35.42 % )
    Info: + Micro hold delay of destination is 0.286 ns
    Info: - Shortest pin to register delay is 3.267 ns
        Info: 1: + IC(0.000 ns) + CELL(1.056 ns) = 1.056 ns; Loc. = PIN_24; Fanout = 13; CLK Node = 'DCLK1'
        Info: 2: + IC(1.631 ns) + CELL(0.580 ns) = 3.267 ns; Loc. = LCFF_X22_Y11_N31; Fanout = 2; REG Node = 'Q1[11]'
        Info: Total cell delay = 1.636 ns ( 50.08 % )
        Info: Total interconnect delay = 1.631 ns ( 49.92 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Fri Mar 14 22:35:31 2008
    Info: Elapsed time: 00:00:02