lianglu.vhd.bak

该程序可是多路频率检测

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;

ENTITY lianglu IS
   PORT (Clr,clk,ENA:IN STD_LOGIC; 
         DCLK1,DCLK2: IN STD_LOGIC;          
         M1,M2:OUT STD_LOGIC); 
END lianglu; 

ARCHITECTURE ONE OF lianglu IS

SIGNAL X1,X2,Q1,Q2:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL LOAD1,LOAD2: STD_LOGIC;

BEGIN

PROCESS(Clr,clk)
      BEGIN   
        IF clr='1' THEN  Q1<="000000000000";
        ELSIF CLK'EVENT AND CLK='1' THEN
                   IF ENA ='1'  THEN  
                           IF DCLK1 = '1' THEN  Q1 <= Q1+1;
                           ELSE   Q1 <= "000000000000"; 
                           END IF;                          
                   END IF;
        END IF;
        LOAD1 <= NOT DCLK1; 
END PROCESS;

PROCESS(Clr,clk)
      BEGIN   
        IF clr='1' THEN  Q2<="000000000000";
        ELSIF CLK'EVENT AND CLK='1' THEN
                   IF ENA ='1'  THEN  
                           IF DCLK2 = '1' THEN  Q2 <= Q2+1;
                           ELSE   Q2 <= "000000000000"; 
                           END IF;                          
                   END IF;
        END IF;
        LOAD2 <= NOT DCLK2; 
END PROCESS;

PROCESS(Q1,CLK)
BEGIN
     IF rising_edge(LOAD1)  THEN  X1 <= Q1 ;                                         
       IF 	X1 > "000011001000"  THEN M1 <='0';
       ELSE    M1 <= '1';
       END IF;
     END IF;
END PROCESS;

PROCESS(Q2,CLK)
BEGIN
     IF rising_edge(LOAD2)  THEN  X2 <= Q2 ;                                         
           IF X2 > "000011001000"  THEN M2 <='0';                
           ELSE    M2 <= '1';
           END IF;
     END IF;
END PROCESS;

END ONE;