📄 kbd.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:49:48 03/20/2007
// Design Name:
// Module Name: kbd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module kbd(kbdclk,kbddat,mclk,rst,dot,ssg,an,key_out);
input kbdclk;
input kbddat;
input mclk;
input rst;
output dot;
output[6:0]ssg;
output[3:0]an;
output[2:0]key_out;
reg an;
reg [5:0]memcnt;
reg [10:0]memhgn;
reg [10:0]mem;
reg [10:0]buffer;
reg [1:0]impulse=0;
reg [3:0]showd;
reg [3:0]showc;
reg [3:0]showb;
reg [3:0]showa;
reg ext;
reg setf0;
reg key_out;
clkdev clkdev1 (mclk,scanclk);
sggctrl sggctrl1 (an,showa,showb,showc,showd,dot,ssg);
always@(negedge kbdclk or posedge rst)
begin
if(rst)
begin
memcnt<=0;
showd<=0;
showc<=11;
showb<=2;
showa<=1;
end
else
begin
mem[memcnt]<=kbddat;
memcnt<=memcnt+1;
if(memcnt==10)
begin
memcnt<=0;
buffer<=mem[8:1];
if(buffer==8'he0) ext<=1;
else if(buffer==8'hf0)
begin
ext<=0;
setf0<=1;
end
else if(setf0==1)setf0<=0;
else if(ext==1)
begin
showd<=4'he;
showc<=4'h0;
showb<=buffer[7:4];
showa<=buffer[3:0];
ext<=0;
if(buffer[7:0]==4'h75) key_out<=1;
else if(buffer[7:0]==4'h74) key_out<=4;
else if(buffer[7:0]==4'h72) key_out<=3;
else if(buffer[7:0]==4'h6b) key_out<=2;
end
else
begin
showd<=4'h0;
showc<=4'h0;
showb<=buffer[7:4];
showa<=buffer[3:0];
end
end
else key_out<=0;
end
end
always@(posedge scanclk)
begin
impulse<=impulse+1;
case(impulse)
2'b00 :an<=4'b1110;
2'b01 :an<=4'b1101;
2'b10 :an<=4'b1011;
2'b11 :an<=4'b0111;
endcase
end
endmodule
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