clkdev.v

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:01:59 03/18/2007 
// Design Name: 
// Module Name:    clkdev 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module clkdev(mclk,scanclk);
input mclk;
output scanclk;


reg scanclk;

reg [19:0]scannum=0;

always@(posedge mclk)
begin
	scannum<=scannum+1;
	if(scannum==10000) 
	begin 
		scannum<=0;
		scanclk<=1;
	end
	else scanclk<=0;
end

/*always@(posedge mclk)
begin
	calnum=calnum+1;
	if(calnum==500000) 
	begin
		calnum=0;
		calclk=1;
	end
	else calclk=0;
end*/

endmodule