kbd_1.v

一个基于FPGA的游戏,其中包含多个项目,有吃豆子,可以连接到LCD的显示输出.该源码用xilinx的ise仿真综合成功,并且用spartan3开发板测试.可以有2个人在键盘上对弈.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:49:48 03/20/2007 
// Design Name: 
// Module Name:    kbd 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module kbd(kbdclk,kbddat,mclk,srt,dot,ssg,an);
input kbdclk;
input kbddat;
input mclk;
input srt;
output dot;
output[6:0]ssg;
output[3:0]an;

reg an;
reg [5:0]memcnt;
reg [10:0]memhgn;
reg [10:0]memlow;
reg [1:0]impulse=0;
reg [3:0]showd;
reg [3:0]showc;
reg [3:0]showb;
reg [3:0]showa;

clkdev clkdev1 (mclk,scanclk);
sggctrl sggctrl1 (an,showa,showb,showc,showd,dot,ssg);
always@(negedge kbdclk or posedge srt)
begin
	if(srt) 
	begin 
		memcnt<=0;
		showd<=0;
		showc<=11;
		showb<=2;
		showa<=1;
	end
	else 
	begin
		memlow[memcnt]<=kbddat;
		memcnt<=memcnt+1;		
		if(memcnt==10)
		begin
			memcnt<=0;
			showd<=memhgn[8:5];
			showc<=memhgn[4:1];
			showb<=memlow[8:5];
			showa<=memlow[4:1];
			memhgn<=memlow;
		end
	end
end

always@(posedge scanclk)
begin
   impulse<=impulse+1;
	case(impulse)
	2'b00 :an<=4'b1110;
	2'b01 :an<=4'b1101;
	2'b10 :an<=4'b1011;
	2'b11 :an<=4'b0111;
	endcase
end

endmodule