layout

C++ 编写的EROS RTOS

/* -*- indented-text -*-  */
/*
 * Copyright (C) 1998, 1999, 2001, Jonathan S. Shapiro.
 *
 * This file is part of the EROS Operating System.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2,
 * or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
 * Register layout for x86.  This file describes both the domain 
 * layout and the save area layout for this architecture.
 *
 * This file is:
 * - processed by GenFixRegs.awk to produce
 *	   eros/(EROS_TARGET)/fixregs.h
 *         which defines fixregs_t (and some masks)
 * - processed by GenFloatRegs.awk to produce
 *         eros/(EROS_TARGET)/floatregs.h
 *         which defines floatregs_t (and some masks)
 * - processed by GenProcOffsets.awk to produce
 *         sys/arch/(EROS_TARGET)/build/(EROS_CONFIG)/process_asm_offsets.h
 *         which defines some offsets in the Process and fixregs_t structures
 *         for assembly code
 * - processed by GenRegMove.awk to produce
 *         sys/arch/(EROS_TARGET)/include/gen.REGMOVE.hxx
 *         which defines macros to move fixed and floating registers
 *         between the process's nodes and the Process structure
 * - processed by GenArchDescrip.awk to produce
 *         cross/lib/erosimg/gen.RegisterDescriptions.cxx
 */

#include <eros/i486/target-asm.h>

/* arch identifies the architecture for the erosimg library. */
arch "i486"

/* unit FPU */

/*
 mask reg  field      bit   bitlen
*/
mask EFLAGS Carry      0     1
mask EFLAGS Parity     3     1
mask EFLAGS AuxCarry   4     1
mask EFLAGS Zero       6     1
mask EFLAGS Sign       7     1
mask EFLAGS Trap       8     1
mask EFLAGS Interrupt  9     1
mask EFLAGS Direction  10    1    
mask EFLAGS Overflow   11    1
mask EFLAGS IOPL       12    2
mask EFLAGS Nested     14    1
mask EFLAGS Resume     16    1
mask EFLAGS Virt8086   17    1
mask EFLAGS AlignCheck 18    1

keysize 16

/*
# NOTE: initially, I thought it sufficient to characterize the
# architecture as big endian or little endian and have done.  This
# doesn't work.  Even on little endian architectures, there are
# registers such as floating point registers whose values may are
# most naturally expressed in big-endian style.
#
# We therefore describe the endianness of all registers
# individually.  What this really means is whether the initialization
# value needs to be reversed before being copied to the register.
*/

/* Here begins a description of the layout of the Process structure.
 * It is used to generate process-asm-offsets.h so assembler code
 * can access fields in that structure.
 * N.B.: It must match the layout defined in C++ in Process.hxx.
 *
 * opaque name type
 *    defines a field which is not referenced in assembler code
 *    (so the name is not used).
 * proc name endian type
 *    defines a field used in assembler code. (endian is not used.)
 * fix ...
 *    defines a field in fixregs_t
 * fpu ...
 *    defines a field in floatregs_t
 * gen ...
 *    defines a field used in assembler code, and also in
 *    ArchDescrip and RegMove.
 */

opaque	kr		KEYRING
proc	stallQ		LTL	SLEEPQ
opaque	isUserContext	uint8_t
opaque	hazards		uint32_t
proc	saveArea	LTL	uint32_t
opaque	cpuReserve	uint32_t
proc	curThread	LTL	uint32_t

/*
 # Following section describes the layout of the save area and how that
 # gets transfered back and forth to the domain root.  It does NOT
 # describe how these values are exported to the end user via the
 # Registers structure, which is described lower down.  The idea here
 # is to capture all of the information required by the EROSIMG library
 # and by various kernel routines.
*/

/*
 * svType is the size in the process node.
 * saType is the size in fixregs_t (for fix) or the Process structure (for gen)
  class name         endian  svType   saType    annex  slot  offset  init-value
*/
fix	ReloadUnits  *       uint32_t uint32_t  *      *     *	     *
fix	MappingTable *       uint32_t uint32_t  *      *     *	     *
fix	EDI	     LTL     uint32_t uint32_t  root   11    4	     "0x0"
fix	ESI	     LTL     uint32_t uint32_t  root   9     4	     "0x0"
fix	EBP	     LTL     uint32_t uint32_t  root   10    8	     "0x0"
fix	ExceptAddr   *       uint32_t uint32_t  *      *     *	     *
fix	EBX	     LTL     uint32_t uint32_t  root   10    4	     "0x0"
fix	EDX	     LTL     uint32_t uint32_t  root   9     0	     "0x0"
fix	ECX	     LTL     uint32_t uint32_t  root   11    0	     "0x0"
fix	EAX	     LTL     uint32_t uint32_t  root   10    0	     "0x0"
fix	ExceptNo     *       uint32_t uint32_t  *      *     *	     *
fix	Error        *       uint32_t uint32_t  *      *     *	     *
/* The program counter must go in root slot 8 offset 0. See eros/Key.h. */
fix	EIP	     LTL     uint32_t uint32_t  root   8     0	     "0x0"
fix	CS	     LTL     uint16_t uint32_t  root   8     8	     "0x23"
fix	EFLAGS       LTL     uint32_t uint32_t  root   12    0	     "0x0200"
/* The stack pointer must go in root slot 8 offset 4. See eros/Key.h. */
fix	ESP	     LTL     uint32_t uint32_t  root   8     4	     "0x0"
fix	SS	     LTL     uint16_t uint32_t  root   8     10	     "0x2b"

proc    INTR_SP      LTL   alias32

fix	ES	     LTL     uint16_t uint32_t  root   11    10	     "0x2b"
fix	DS	     LTL     uint16_t uint32_t  root   11    8	     "0x2b"
fix	FS	     LTL     uint16_t uint32_t  root   9     8	     "0x2b"
fix	GS	     LTL     uint16_t uint32_t  root   9     10	     "0x2b"

proc    V86_INTR_SP  LTL   alias32

fix	invType	     LTL     uint32_t uint32_t  root   10    0       "0x0"
fix	invKey	     LTL     uint32_t uint32_t  root   10    4       "0x0"
fix	sndLen	     LTL     uint32_t uint32_t  root   10    8       "0x0"
fix	sndPtr       LTL     uint32_t uint32_t  root   14    0       "0x0"
fix	sndKeys	     LTL     uint32_t uint32_t  root   14    4       "0x0"
fix	rcvKeys      LTL     uint32_t uint32_t  root   14    8       "0x0"

#if 0
# following are pseudo-registers:
stat	hiEvtCount   LTL     uint32_t uint32_t  root   12    4	     "0x0"
stat	loEvtCount   LTL     uint32_t uint32_t  root   12    8	     "0x0"
stat	pfCount      LTL     uint32_t uint32_t  root   12    8	     "0x0"
#endif

proc    keyregs      *       KEYREGS

gen	faultCode    LTL     uint32_t uint32_t  root   7     0       "0x0"
gen	faultInfo    LTL     uint32_t uint32_t  root   7     4       "0x0"
gen	runState     LTL     uint8_t  uint8_t   root   7     8       "0x0"
gen	processFlags LTL     uint8_t  uint8_t   root   7     9       "0x0"

#ifdef OPTION_SMALL_SPACES
/*
 * Following may not actually be present, but if present they appear 
 * at this offset:
 */
proc	limit        LTL     uint32_t
proc	bias         LTL     uint32_t
#endif


fpmask FPSTATUS EXCEPTIONS   0     6
fpmask FPSTATUS Invalid      0     1
fpmask FPSTATUS Denormal     1     1
fpmask FPSTATUS ZeroDivide   2     1
fpmask FPSTATUS Overflow     3     1
fpmask FPSTATUS Underflow    4     1
fpmask FPSTATUS Precision    5     1
fpmask FPSTATUS StackFault   6     1
fpmask FPSTATUS ErrorSummary 7     1
fpmask FPSTATUS C0           8     1
fpmask FPSTATUS C1           9     1
fpmask FPSTATUS C2           10    1
fpmask FPSTATUS Top          11    3
fpmask FPSTATUS C3           14    1
fpmask FPSTATUS Busy         15    1

/* 
 * The order of appearance for these values is dictated by the layout 
 * of the hardware floating point save area.  The state established
 * here is identical to that established by the FNINIT instruction,
 * with the exception that the FDS/FCS registers are set to the
 * appropriate segment selectors.
 */
fpu  	f_ctrl	     LTL     uint16_t uint32_t  root   24    10      "0x37f"
fpu  	f_status     LTL     uint16_t uint32_t  root   24    8       "0x0"
fpu  	f_tag	     LTL     uint16_t uint32_t  root   24    6       "0xffff"
fpu  	f_ip	     LTL     uint32_t uint32_t  root   25    0       "0x0"
fpu  	f_cs	     LTL     uint16_t uint16_t  root   25    4	     "0x23"
fpu  	f_opcode     LTL     uint16_t uint16_t  root   25    6	     "0x0"
fpu  	f_dp	     LTL     uint32_t uint32_t  root   24    0       "0x0"
fpu  	f_ds	     LTL     uint16_t uint32_t  root   24    4	     "0x2b"


fpu  	f_r0	     BIG     uint80_t uint80_t  root   16    0       "0x0"
fpu  	f_r1	     BIG     uint80_t uint80_t  root   17    0       "0x0"
fpu  	f_r2	     BIG     uint80_t uint80_t  root   18    0       "0x0"
fpu  	f_r3	     BIG     uint80_t uint80_t  root   19    0       "0x0"
fpu  	f_r4	     BIG     uint80_t uint80_t  root   20    0       "0x0"
fpu  	f_r5	     BIG     uint80_t uint80_t  root   21    0       "0x0"
fpu  	f_r6	     BIG     uint80_t uint80_t  root   22    0       "0x0"
fpu  	f_r7	     BIG     uint80_t uint80_t  root   23    0       "0x0"