as.1

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.IP "\fB\-\-print\-insn\-syntax\fR" 4
.IX Item "--print-insn-syntax"
Print the syntax of instruction in case of error.
.IP "\fB\-\-print\-opcodes\fR" 4
.IX Item "--print-opcodes"
print the list of instructions with syntax and then exit.
.IP "\fB\-\-generate\-example\fR" 4
.IX Item "--generate-example"
print an example of instruction for each possible instruction and then exit.
This option is only useful for testing \fBas\fR.
.PP
The following options are available when \fBas\fR is configured
for the \s-1SPARC\s0 architecture:
.IP "\fB\-Av6 | \-Av7 | \-Av8 | \-Asparclet | \-Asparclite\fR" 4
.IX Item "-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite"
.PD 0
.IP "\fB\-Av8plus | \-Av8plusa | \-Av9 | \-Av9a\fR" 4
.IX Item "-Av8plus | -Av8plusa | -Av9 | -Av9a"
.PD
Explicitly select a variant of the \s-1SPARC\s0 architecture.
.Sp
\&\fB\-Av8plus\fR and \fB\-Av8plusa\fR select a 32 bit environment.
\&\fB\-Av9\fR and \fB\-Av9a\fR select a 64 bit environment.
.Sp
\&\fB\-Av8plusa\fR and \fB\-Av9a\fR enable the \s-1SPARC\s0 V9 instruction set with
UltraSPARC extensions.
.IP "\fB\-xarch=v8plus | \-xarch=v8plusa\fR" 4
.IX Item "-xarch=v8plus | -xarch=v8plusa"
For compatibility with the Solaris v9 assembler.  These options are
equivalent to \-Av8plus and \-Av8plusa, respectively.
.IP "\fB\-bump\fR" 4
.IX Item "-bump"
Warn when the assembler switches to another architecture.
.PP
The following options are available when as is configured for the 'c54x
architecture. 
.IP "\fB\-mfar\-mode\fR" 4
.IX Item "-mfar-mode"
Enable extended addressing mode.  All addresses and relocations will assume
extended addressing (usually 23 bits).
.IP "\fB\-mcpu=\fR\fI\s-1CPU_VERSION\s0\fR" 4
.IX Item "-mcpu=CPU_VERSION"
Sets the \s-1CPU\s0 version being compiled for.
.IP "\fB\-merrors\-to\-file\fR \fI\s-1FILENAME\s0\fR" 4
.IX Item "-merrors-to-file FILENAME"
Redirect error output to a file, for broken systems which don't support such
behaviour in the shell.
.PP
The following options are available when as is configured for
a \s-1MIPS\s0 processor.
.IP "\fB\-G\fR \fInum\fR" 4
.IX Item "-G num"
This option sets the largest size of an object that can be referenced
implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targets that
use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Generate \*(L"big endian\*(R" format output.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Generate \*(L"little endian\*(R" format output.
.IP "\fB\-mips1\fR" 4
.IX Item "-mips1"
.PD 0
.IP "\fB\-mips2\fR" 4
.IX Item "-mips2"
.IP "\fB\-mips3\fR" 4
.IX Item "-mips3"
.IP "\fB\-mips4\fR" 4
.IX Item "-mips4"
.IP "\fB\-mips5\fR" 4
.IX Item "-mips5"
.IP "\fB\-mips32\fR" 4
.IX Item "-mips32"
.IP "\fB\-mips32r2\fR" 4
.IX Item "-mips32r2"
.IP "\fB\-mips64\fR" 4
.IX Item "-mips64"
.IP "\fB\-mips64r2\fR" 4
.IX Item "-mips64r2"
.PD
Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
\&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
\&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
\&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips64\fR, and
\&\fB\-mips64r2\fR
correspond to generic
\&\fB\s-1MIPS\s0 V\fR, \fB\s-1MIPS32\s0\fR, \fB\s-1MIPS32\s0 Release 2\fR, \fB\s-1MIPS64\s0\fR,
and \fB\s-1MIPS64\s0 Release 2\fR
\&\s-1ISA\s0 processors, respectively.
.IP "\fB\-march=\fR\fI\s-1CPU\s0\fR" 4
.IX Item "-march=CPU"
Generate code for a particular \s-1MIPS\s0 cpu.
.IP "\fB\-mtune=\fR\fIcpu\fR" 4
.IX Item "-mtune=cpu"
Schedule and tune for a particular \s-1MIPS\s0 cpu.
.IP "\fB\-mfix7000\fR" 4
.IX Item "-mfix7000"
.PD 0
.IP "\fB\-mno\-fix7000\fR" 4
.IX Item "-mno-fix7000"
.PD
Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two instructions.
.IP "\fB\-mdebug\fR" 4
.IX Item "-mdebug"
.PD 0
.IP "\fB\-no\-mdebug\fR" 4
.IX Item "-no-mdebug"
.PD
Cause stabs-style debugging output to go into an ECOFF-style .mdebug
section instead of the standard \s-1ELF\s0 .stabs sections.
.IP "\fB\-mpdr\fR" 4
.IX Item "-mpdr"
.PD 0
.IP "\fB\-mno\-pdr\fR" 4
.IX Item "-mno-pdr"
.PD
Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
.IP "\fB\-mgp32\fR" 4
.IX Item "-mgp32"
.PD 0
.IP "\fB\-mfp32\fR" 4
.IX Item "-mfp32"
.PD
The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these
flags force a certain group of registers to be treated as 32 bits wide at
all times.  \fB\-mgp32\fR controls the size of general-purpose registers
and \fB\-mfp32\fR controls the size of floating-point registers.
.IP "\fB\-mips16\fR" 4
.IX Item "-mips16"
.PD 0
.IP "\fB\-no\-mips16\fR" 4
.IX Item "-no-mips16"
.PD
Generate code for the \s-1MIPS\s0 16 processor.  This is equivalent to putting
\&\f(CW\*(C`.set mips16\*(C'\fR at the start of the assembly file.  \fB\-no\-mips16\fR
turns off this option.
.IP "\fB\-msmartmips\fR" 4
.IX Item "-msmartmips"
.PD 0
.IP "\fB\-mno\-smartmips\fR" 4
.IX Item "-mno-smartmips"
.PD
Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set. This is
equivalent to putting \f(CW\*(C`.set smartmips\*(C'\fR at the start of the assembly file.
\&\fB\-mno\-smartmips\fR turns off this option.
.IP "\fB\-mips3d\fR" 4
.IX Item "-mips3d"
.PD 0
.IP "\fB\-no\-mips3d\fR" 4
.IX Item "-no-mips3d"
.PD
Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
\&\fB\-no\-mips3d\fR turns off this option.
.IP "\fB\-mdmx\fR" 4
.IX Item "-mdmx"
.PD 0
.IP "\fB\-no\-mdmx\fR" 4
.IX Item "-no-mdmx"
.PD
Generate code for the \s-1MDMX\s0 Application Specific Extension.
This tells the assembler to accept \s-1MDMX\s0 instructions.
\&\fB\-no\-mdmx\fR turns off this option.
.IP "\fB\-mdsp\fR" 4
.IX Item "-mdsp"
.PD 0
.IP "\fB\-mno\-dsp\fR" 4
.IX Item "-mno-dsp"
.PD
Generate code for the \s-1DSP\s0 Application Specific Extension.
This tells the assembler to accept \s-1DSP\s0 instructions.
\&\fB\-mno\-dsp\fR turns off this option.
.IP "\fB\-mmt\fR" 4
.IX Item "-mmt"
.PD 0
.IP "\fB\-mno\-mt\fR" 4
.IX Item "-mno-mt"
.PD
Generate code for the \s-1MT\s0 Application Specific Extension.
This tells the assembler to accept \s-1MT\s0 instructions.
\&\fB\-mno\-mt\fR turns off this option.
.IP "\fB\-\-construct\-floats\fR" 4
.IX Item "--construct-floats"
.PD 0
.IP "\fB\-\-no\-construct\-floats\fR" 4
.IX Item "--no-construct-floats"
.PD
The \fB\-\-no\-construct\-floats\fR option disables the construction of
double width floating point constants by loading the two halves of the
value into the two single width floating point registers that make up
the double width register.  By default \fB\-\-construct\-floats\fR is
selected, allowing construction of these floating point constants.
.IP "\fB\-\-emulation=\fR\fIname\fR" 4
.IX Item "--emulation=name"
This option causes \fBas\fR to emulate \fBas\fR configured
for some other target, in all respects, including output format (choosing
between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate
debugging information or store symbol table information, and default
endianness.  The available configuration names are: \fBmipsecoff\fR,
\&\fBmipself\fR, \fBmipslecoff\fR, \fBmipsbecoff\fR, \fBmipslelf\fR,
\&\fBmipsbelf\fR.  The first two do not alter the default endianness from that
of the primary target for which the assembler was configured; the others change
the default to little\- or big-endian as indicated by the \fBb\fR or \fBl\fR
in the name.  Using \fB\-EB\fR or \fB\-EL\fR will override the endianness
selection in any case.
.Sp
This option is currently supported only when the primary target
\&\fBas\fR is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target.
Furthermore, the primary target or others specified with
\&\fB\-\-enable\-targets=...\fR at configuration time must include support for
the other format, if both are to be available.  For example, the Irix 5
configuration includes support for both.
.Sp
Eventually, this option will support more configurations, with more
fine-grained control over the assembler's behavior, and will be supported for
more processors.
.IP "\fB\-nocpp\fR" 4
.IX Item "-nocpp"
\&\fBas\fR ignores this option.  It is accepted for compatibility with
the native tools.
.IP "\fB\-\-trap\fR" 4
.IX Item "--trap"
.PD 0
.IP "\fB\-\-no\-trap\fR" 4
.IX Item "--no-trap"
.IP "\fB\-\-break\fR" 4
.IX Item "--break"
.IP "\fB\-\-no\-break\fR" 4
.IX Item "--no-break"
.PD
Control how to deal with multiplication overflow and division by zero.
\&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
(and only work for Instruction Set Architecture level 2 and higher);
\&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
break exception.
.IP "\fB\-n\fR" 4
.IX Item "-n"
When this option is used, \fBas\fR will issue a warning every
time it generates a nop instruction from a macro.
.PP
The following options are available when as is configured for
an MCore processor.
.IP "\fB\-jsri2bsr\fR" 4
.IX Item "-jsri2bsr"
.PD 0
.IP "\fB\-nojsri2bsr\fR" 4
.IX Item "-nojsri2bsr"
.PD
Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation.  By default this is enabled.
The command line option \fB\-nojsri2bsr\fR can be used to disable it.
.IP "\fB\-sifilter\fR" 4
.IX Item "-sifilter"
.PD 0
.IP "\fB\-nosifilter\fR" 4
.IX Item "-nosifilter"
.PD
Enable or disable the silicon filter behaviour.  By default this is disabled.
The default can be overridden by the \fB\-sifilter\fR command line option.
.IP "\fB\-relax\fR" 4
.IX Item "-relax"
Alter jump instructions for long displacements.
.IP "\fB\-mcpu=[210|340]\fR" 4
.IX Item "-mcpu=[210|340]"
Select the cpu type on the target hardware.  This controls which instructions
can be assembled.
.IP "\fB\-EB\fR" 4
.IX Item "-EB"
Assemble for a big endian target.
.IP "\fB\-EL\fR" 4
.IX Item "-EL"
Assemble for a little endian target.
.PP
See the info pages for documentation of the MMIX-specific options.
.PP
The following options are available when as is configured for
an Xtensa processor.
.IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
.IX Item "--text-section-literals | --no-text-section-literals"
With \fB\-\-text\-section\-literals\fR, literal pools are interspersed
in the text section.  The default is
\&\fB\-\-no\-text\-section\-literals\fR, which places literals in a
separate section in the output file.  These options only affect literals
referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for
absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
.IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
.IX Item "--absolute-literals | --no-absolute-literals"
Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
or PC-relative addressing.  The default is to assume absolute addressing
if the Xtensa processor includes the absolute \f(CW\*(C`L32R\*(C'\fR addressing
option.  Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR mode can be used.
.IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
.IX Item "--target-align | --no-target-align"
Enable or disable automatic alignment to reduce branch penalties at the
expense of some code density.  The default is \fB\-\-target\-align\fR.
.IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
.IX Item "--longcalls | --no-longcalls"
Enable or disable transformation of call instructions to allow calls
across a greater range of addresses.  The default is
\&\fB\-\-no\-longcalls\fR.
.IP "\fB\-\-transform | \-\-no\-transform\fR" 4
.IX Item "--transform | --no-transform"
Enable or disable all assembler transformations of Xtensa instructions.
The default is \fB\-\-transform\fR;
\&\fB\-\-no\-transform\fR should be used only in the rare cases when the
instructions must be exactly as specified in the assembly source.
.PP
The following options are available when as is configured for
a Z80 family processor.
.IP "\fB\-z80\fR" 4
.IX Item "-z80"
Assemble for Z80 processor.
.IP "\fB\-r800\fR" 4
.IX Item "-r800"
Assemble for R800 processor.
.IP "\fB\-ignore\-undocumented\-instructions\fR" 4
.IX Item "-ignore-undocumented-instructions"
.PD 0
.IP "\fB\-Wnud\fR" 4
.IX Item "-Wnud"
.PD
Assemble undocumented Z80 instructions that also work on R800 without warning.
.IP "\fB\-ignore\-unportable\-instructions\fR" 4
.IX Item "-ignore-unportable-instructions"
.PD 0
.IP "\fB\-Wnup\fR" 4
.IX Item "-Wnup"
.PD
Assemble all undocumented Z80 instructions without warning.
.IP "\fB\-warn\-undocumented\-instructions\fR" 4
.IX Item "-warn-undocumented-instructions"
.PD 0
.IP "\fB\-Wud\fR" 4
.IX Item "-Wud"
.PD
Issue a warning for undocumented Z80 instructions that also work on R800.
.IP "\fB\-warn\-unportable\-instructions\fR" 4
.IX Item "-warn-unportable-instructions"
.PD 0
.IP "\fB\-Wup\fR" 4
.IX Item "-Wup"
.PD
Issue a warning for undocumented Z80 instructions that do not work on R800.  
.IP "\fB\-forbid\-undocumented\-instructions\fR" 4
.IX Item "-forbid-undocumented-instructions"
.PD 0
.IP "\fB\-Fud\fR" 4
.IX Item "-Fud"
.PD
Treat all undocumented instructions as errors.
.IP "\fB\-forbid\-unportable\-instructions\fR" 4
.IX Item "-forbid-unportable-instructions"
.PD 0
.IP "\fB\-Fup\fR" 4
.IX Item "-Fup"
.PD
Treat undocumented Z80 instructions that do not work on R800 as errors.
.SH "SEE ALSO"
.IX Header "SEE ALSO"
\&\fIgcc\fR\|(1), \fIld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002, 2006 Free Software Foundation, Inc.
.PP
Permission is granted to copy, distribute and/or modify this document
under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1
or any later version published by the Free Software Foundation;
with no Invariant Sections, with no Front-Cover Texts, and with no
Back-Cover Texts.  A copy of the license is included in the
section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".