📄 dspboard.asm
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MOV AC0, dbl(*(#(_myUsbConfig+8)))
.line 12
CALL #_EnableAPLL ; |242|
; call occurs [#_EnableAPLL] ; |242|
.line 13
CALL #_USB_setAPIVectorAddress ; |243|
; call occurs [#_USB_setAPIVectorAddress] ; |243|
.line 15
MOV #0, T0
AMOV #_myUsbConfig, XAR0 ; |245|
MOV #0, T1
CALL #_vUSB_init ; |245|
; call occurs [#_vUSB_init] ; |245|
.line 18
AMOV #4194304, XAR3 ; |248|
MOV XAR3, dbl(*(#_sourceAddr))
.line 30
MOV #13312, AR3 ; |260|
MOV #127, port(*AR3) ; |260|
.line 31
MOV #13313, AR3 ; |261|
MOV port(*AR3), AR1 ; |261|
OR #0x0030, AR1, AR1 ; |261|
AND #0x00b7, AR1, AR1 ; |261|
MOV AR1, port(*AR3) ; |261|
.line 34
MOV #3, T0
CALL #_IRQ_enable ; |264|
; call occurs [#_IRQ_enable] ; |264|
.line 36
MOV #8, T0
CALL #_IRQ_clear ; |266|
; call occurs [#_IRQ_clear] ; |266|
.line 37
MOV #8, T0
CALL #_IRQ_enable ; |267|
; call occurs [#_IRQ_enable] ; |267|
.line 39
MOV #18, T0 ; |269|
CALL #_IRQ_enable ; |269|
; call occurs [#_IRQ_enable] ; |269|
.line 40
MOV #9, T0
CALL #_IRQ_enable ; |270|
; call occurs [#_IRQ_enable] ; |270|
.line 41
MOV #20, T0 ; |271|
CALL #_IRQ_enable ; |271|
; call occurs [#_IRQ_enable] ; |271|
.line 43
MOV #22, T0 ; |273|
CALL #_IRQ_enable ; |273|
; call occurs [#_IRQ_enable] ; |273|
.line 45
MOV #1, *(#_bCollectingIsOn) ; |275|
.line 51
CALL #_IRQ_globalEnable ; |281|
; call occurs [#_IRQ_globalEnable] ; |281|
.line 56
MOV #0, T0
CALL #_vUSB_connectDev ; |286|
; call occurs [#_vUSB_connectDev] ; |286|
.line 58
MOV dbl(*(#_hTimer1)), XAR0
CALL #_TIMER_start ; |288|
; call occurs [#_TIMER_start] ; |288|
.line 60
MOV #13313, AR3 ; |290|
MOV port(*AR3), AR1 ; |290|
OR #0x0042, AR1, AR1 ; |290|
MOV AR1, port(*AR3) ; |290|
.line 63
MOV #1000, *(#_nDataIOcount) ; |293|
.line 67
.line 70
B L20 ; |300|
; branch occurs ; |300|
L15:
.line 73
MOV *(#_bDMA0On), AR1 ; |303|
BCC L20,AR1 != #0 ; |303|
; branch occurs ; |303|
.line 74
CALL #_Buffer0Processing ; |304|
; call occurs [#_Buffer0Processing] ; |304|
B L20 ; |304|
; branch occurs ; |304|
L16:
.line 77
MOV *(#_bDMA1On), AR1 ; |307|
BCC L20,AR1 != #0 ; |307|
; branch occurs ; |307|
.line 78
CALL #_Buffer1Processing ; |308|
; call occurs [#_Buffer1Processing] ; |308|
B L20 ; |308|
; branch occurs ; |308|
L17:
.line 82
MOV *(#_bDMA0On), AR1 ; |312|
BCC L18,AR1 != #0 ; |312|
; branch occurs ; |312|
.line 83
CALL #_Buffer0Processing ; |313|
; call occurs [#_Buffer0Processing] ; |313|
L18:
.line 84
MOV *(#_bDMA1On), AR1 ; |314|
BCC L20,AR1 != #0 ; |314|
; branch occurs ; |314|
.line 85
CALL #_Buffer1Processing ; |315|
; call occurs [#_Buffer1Processing] ; |315|
B L20 ; |315|
; branch occurs ; |315|
L19:
.line 90
AMOV #_TSK_timerSem, XAR0 ; |320|
MOV #2, T0
CALL #_SEM_pend ; |320|
; call occurs [#_SEM_pend] ; |320|
L20:
.line 70
MOV *(#_iBufferReady), AR1 ; |300|
MOV #1, AR2
AND #0x0003, AR1, AR1 ; |300|
CMPU AR1 == AR2, TC1 ; |300|
|| NOP ; avoids Silicon Exception CPU_24
BCC L15,TC1 ; |300|
; branch occurs ; |300|
MOV #2, AR2
CMPU AR1 == AR2, TC1 ; |300|
|| NOP ; avoids Silicon Exception CPU_24
BCC L16,TC1 ; |300|
; branch occurs ; |300|
MOV #3, AR2
CMPU AR1 == AR2, TC1 ; |300|
|| NOP ; avoids Silicon Exception CPU_24
BCC L17,TC1 ; |300|
; branch occurs ; |300|
B L19 ; |300|
; branch occurs ; |300|
.endfunc 324,000000000h,3
.sect ".text"
.align 4
.global _readyReadFIFO
.sym _readyReadFIFO,_readyReadFIFO, 32, 2, 0
.func 327
;*******************************************************************************
;* FUNCTION NAME: _readyReadFIFO *
;* *
;* Function Uses Regs : AC0,AC0,AR0,XAR0,AR1,AR2,SP,CARRY,TC1,M40,SATA,SATD, *
;* RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 2 words *
;* (2 return address/alignment) *
;*******************************************************************************
_readyReadFIFO:
.line 2
AADD #-1, SP
.line 6
B L27 ; |332|
; branch occurs ; |332|
L21:
.line 10
MOV *(#_bDMA0On), AR1 ; |336|
BCC L22,AR1 != #0 ; |336|
; branch occurs ; |336|
.line 13
OR #0x0001, *(#_iBufferReady) ; |339|
.line 14
MOV #1, *(#_bDMA0On) ; |340|
.line 15
MOV dbl(*(#_hDma0)), XAR0
CALL #_DMA_start ; |341|
; call occurs [#_DMA_start] ; |341|
.line 16
MOV dbl(*(#_nRecordDMA0Miss)), AC0 ; |342|
ADD #1, AC0 ; |342|
MOV AC0, dbl(*(#_nRecordDMA0Miss)) ; |342|
.line 17
B L28 ; |343|
; branch occurs ; |343|
L22:
.line 20
MOV dbl(*(#_nRecordDMA0Miss)), AC0 ; |346|
ADD #1, AC0 ; |346|
MOV AC0, dbl(*(#_nRecordDMA0Miss)) ; |346|
.line 21
B L28 ; |347|
; branch occurs ; |347|
L23:
.line 24
MOV *(#_bDMA1On), AR1 ; |350|
BCC L24,AR1 != #0 ; |350|
; branch occurs ; |350|
.line 26
OR #0x0002, *(#_iBufferReady) ; |352|
.line 27
MOV #1, *(#_bDMA1On) ; |353|
.line 28
MOV dbl(*(#_hDma1)), XAR0
CALL #_DMA_start ; |354|
; call occurs [#_DMA_start] ; |354|
.line 29
MOV dbl(*(#_nRecordDMA1Miss)), AC0 ; |355|
ADD #1, AC0 ; |355|
MOV AC0, dbl(*(#_nRecordDMA1Miss)) ; |355|
.line 30
B L28 ; |356|
; branch occurs ; |356|
L24:
.line 33
MOV dbl(*(#_nRecordDMA1Miss)), AC0 ; |359|
ADD #1, AC0 ; |359|
MOV AC0, dbl(*(#_nRecordDMA1Miss)) ; |359|
.line 34
B L28 ; |360|
; branch occurs ; |360|
L25:
.line 38
MOV *(#_bDMA2On), AR1 ; |364|
BCC L26,AR1 != #0 ; |364|
; branch occurs ; |364|
.line 40
MOV #1, *(#_bDMA2On) ; |366|
.line 41
MOV dbl(*(#_hDma2)), XAR0
CALL #_DMA_start ; |367|
; call occurs [#_DMA_start] ; |367|
.line 42
MOV dbl(*(#_nRecordMissed)), AC0 ; |368|
ADD #1, AC0 ; |368|
MOV AC0, dbl(*(#_nRecordMissed)) ; |368|
.line 43
B L28 ; |369|
; branch occurs ; |369|
L26:
.line 46
MOV dbl(*(#_nRecordMissed)), AC0 ; |372|
ADD #1, AC0 ; |372|
MOV AC0, dbl(*(#_nRecordMissed)) ; |372|
.line 47
MOV dbl(*(#_nRecordDMA2Miss)), AC0 ; |373|
ADD #1, AC0 ; |373|
MOV AC0, dbl(*(#_nRecordDMA2Miss)) ; |373|
.line 48
B L28 ; |374|
; branch occurs ; |374|
L27:
.line 6
MOV *(#_iBufferReady), AR1 ; |332|
AND #0x0003, AR1, AR1 ; |332|
BCC L21,AR1 == #0 ; |332|
; branch occurs ; |332|
MOV #1, AR2
CMPU AR1 == AR2, TC1 ; |332|
|| NOP ; avoids Silicon Exception CPU_24
BCC L23,TC1 ; |332|
; branch occurs ; |332|
MOV #2, AR2
CMPU AR1 == AR2, TC1 ; |332|
|| NOP ; avoids Silicon Exception CPU_24
BCC L21,TC1 ; |332|
; branch occurs ; |332|
B L25 ; |332|
; branch occurs ; |332|
L28:
.line 53
AADD #1, SP
RET
; return occurs
.endfunc 379,000000000h,1
.sect ".text"
.align 4
.global _TransferDMA0
.sym _TransferDMA0,_TransferDMA0, 32, 2, 0
.func 382
;*******************************************************************************
;* FUNCTION NAME: _TransferDMA0 *
;* *
;* Function Uses Regs : SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;*******************************************************************************
_TransferDMA0:
.line 2
.line 3
MOV #0, *(#_bDMA0On) ; |384|
.line 4
RET
; return occurs
.endfunc 385,000000000h,0
.sect ".text"
.align 4
.global _TransferDMA1
.sym _TransferDMA1,_TransferDMA1, 32, 2, 0
.func 387
;*******************************************************************************
;* FUNCTION NAME: _TransferDMA1 *
;* *
;* Function Uses Regs : SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;*******************************************************************************
_TransferDMA1:
.line 2
.line 3
MOV #0, *(#_bDMA1On) ; |389|
.line 4
RET
; return occurs
.endfunc 390,000000000h,0
.sect ".text"
.align 4
.global _TransferDMA2
.sym _TransferDMA2,_TransferDMA2, 32, 2, 0
.func 392
;*******************************************************************************
;* FUNCTION NAME: _TransferDMA2 *
;* *
;* Function Uses Regs : SP,M40,SATA,SATD,RDM,FRCT,SMUL *
;* Stack Frame : Compact (No Frame Pointer, w/ debug) *
;* Total Frame Size : 1 word *
;* (1 return address/alignment) *
;*******************************************************************************
_TransferDMA2:
.line 2
.line 3
MOV #0, *(#_bDMA2On) ; |394|
.line 4
RET
; return occurs
.endfunc 395,000000000h,0
.sect ".text"
.align 4
.global _readFIFO
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