muxb_mb.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity MUXB is
  
  port (
    constant_in : in std_logic_vector(15 downto 0);
    B_data      : in std_logic_vector(15 downto 0);
    MB         : in std_logic;
    BUS_B      : out std_logic_vector(15 downto 0));

end MUXB;


architecture rtl of MUXB is

begin  -- rtl
process(constant_in,B_data,MB)
  begin
    case MB is
      when '0' => BUS_B<= B_data ;
      when '1'=> BUS_B<=constant_in;
      when others => null;
    end case;
  end process;

end rtl;