top1_test.vhd

thats the CPU source made by JI FENG

library ieee;
use ieee.std_logic_1164.all;

entity test_top1 is
  
end test_top1;

architecture tb_test_top1 of test_top1 is

component TOP1
  port(
    clk         : in  std_logic;
    AA, BA, DA  : in  std_logic_vector(2 downto 0);
    RW          : in  std_logic;
    Data_in     : in  std_logic_vector(15 downto 0);
    constant_in : in  std_logic_vector(15 downto 0);
    MB          : in  std_logic;        -- FS
    FS          : in  std_logic_vector(3 downto 0);
    MD          : in  std_logic;
    V, C, N, Z  : out std_logic;
    data_out    : out std_logic_vector(15 downto 0);
    address_out  : out std_logic_vector(15 downto 0));
end component;
signal clk : std_logic:='0';
signal AA,BA,DA : std_logic_vector(2 downto 0);
signal RW : std_logic;
signal data_in : std_logic_vector(15 downto 0);
signal constant_in : std_logic_vector(15 downto 0);
signal MB : std_logic;
signal fs : std_logic_vector(3 downto 0);
signal MD : std_logic;
signal V,C,N,Z : std_logic;
signal data_out : std_logic_vector(15 downto 0);
signal address_out : std_logic_vector(15 downto 0);



begin  -- tb_test_top1

uTOP1 : TOP1 port map (
  CLK         => CLK,
  AA          => AA,
  BA          => BA,
  DA          => DA,
  RW          => RW,
  Data_in     => Data_in,
  constant_in => constant_in,
  MB          => MB,
  fs          => fs,
  MD          => MD,
  V           => V,
  C           => c ,
  Z           => Z,
  N           => N,
  data_out    => data_out,
  address_out => address_out);
  

clk<=not(clk) after 50 ns;


  
DATA_IN<="0000000000001111";
MB<='0';
MD<='0';
RW<='1';
AA<="001" after 50 ns;
BA<="010" after 50 ns;
FS<="0010" after 50 ns;


end tb_test_top1;