s12_pim.h

PWM Generation Using HCS12 Timer Channels

#define RDRM0	0x01	/*bit masks */
#define RDRM1	0x02
#define RDRM2	0x04
#define RDRM3	0x08
#define RDRM4	0x10
#define RDRM5	0x20
#define RDRM6	0x40
#define RDRM7	0x80

typedef union uPERM		/*pull-up/dn enable register */
  {
  tU08	byte;
  struct
    {
    tU08 perm0	:1;		/*pull-up/dn bits (1:enabled) */
    tU08 perm1	:1;
    tU08 perm2	:1;
    tU08 perm3	:1;
    tU08 perm4	:1;
    tU08 perm5	:1;
    tU08 perm6	:1;
    tU08 perm7	:1;
    }bit;
  }tPERM;

#define PERM0	0x01	/*bit masks */
#define PERM1	0x02
#define PERM2 	0x04
#define PERM3 	0x08
#define PERM4 	0x10
#define PERM5 	0x20
#define PERM6 	0x40
#define PERM7 	0x80

typedef union uPPSM		/*pull-up/dn polarity register */
  {
  tU08	byte;
  struct
    {
    tU08 ppsm0	:1;		/*pull-up/dn bits (0:pull-up;1:pull-dn) */
    tU08 ppsm1	:1;
    tU08 ppsm2	:1;
    tU08 ppsm3	:1;
    tU08 ppsm4	:1;
    tU08 ppsm5	:1;
    tU08 ppsm6	:1;
    tU08 ppsm7	:1;
    }bit;
  }tPPSM;

#define PPSM0	0x01	/*bit masks */
#define PPSM1	0x02
#define PPSM2 	0x04
#define PPSM3 	0x08
#define PPSM4 	0x10
#define PPSM5 	0x20
#define PPSM6 	0x40
#define PPSM7 	0x80

typedef union uWOMM		/*wired-or mode register */
  {
  tU08	byte;
  struct
    {
    tU08 womm0	:1;		/*wired-or bits (1:enabled) */
    tU08 womm1	:1;
    tU08 womm2	:1;
    tU08 womm3	:1;
    tU08 womm4	:1;
    tU08 womm5	:1;
    tU08 womm6	:1;
    tU08 womm7	:1;
    }bit;
  }tWOMM;

#define WOMM0	0x01	/*bit masks */
#define WOMM1	0x02
#define WOMM2 	0x04
#define WOMM3 	0x08
#define WOMM4 	0x10
#define WOMM5 	0x20
#define WOMM6 	0x40
#define WOMM7 	0x80


/******************** Module Routing Register MODRR ***************/

typedef union uMODRR
  {
  tU08	byte;
  struct
    {
    tU08 modrr0	:1;		/*CAN0 routing */
    tU08 modrr1	:1;		/*CAN0 routing */
    tU08 modrr2	:1;		/*CAN4 routing */
    tU08 modrr3	:1;		/*CAN4 routing */
    tU08 modrr4	:1;		/*SPI0 routing */
    tU08 modrr5	:1;		/*SPI1 routing */
    tU08 modrr6	:1;		/*SPI2 routing */
    tU08        :1;		/*not used */
    }bit;
  }tMODRR;

#define MODRR0	0x01	/*bit masks */
#define MODRR1	0x02
#define MODRR2	0x04
#define MODRR3	0x08
#define MODRR4	0x10
#define MODRR5	0x20
#define MODRR6	0x40


/******************************  PORT P  **************************/

typedef union uPTP		/*i/o register */
  {
  tU08	byte;
  struct
    {
    tU08 ptp0	:1;		/*i/o port pins */
    tU08 ptp1	:1;
    tU08 ptp2	:1;
    tU08 ptp3	:1;
    tU08 ptp4	:1;
    tU08 ptp5	:1;
    tU08 ptp6	:1;
    tU08 ptp7	:1;
    }bit;
  }tPTP;

#define PTP0	0x01	/*bit masks */
#define PTP1	0x02
#define PTP2 	0x04
#define PTP3 	0x08
#define PTP4 	0x10
#define PTP5 	0x20
#define PTP6 	0x40
#define PTP7 	0x80

typedef union uPTIP		/*input register */
  {
  tU08	byte;
  struct
    {
    tU08 ptip0	:1;		/*i/o port pins */
    tU08 ptip1	:1;
    tU08 ptip2	:1;
    tU08 ptip3	:1;
    tU08 ptip4	:1;
    tU08 ptip5	:1;
    tU08 ptip6	:1;
    tU08 ptip7	:1;
    }bit;
  }tPTIP;

#define PTIP0	0x01	/*bit masks */
#define PTIP1	0x02
#define PTIP2 	0x04
#define PTIP3 	0x08
#define PTIP4 	0x10
#define PTIP5 	0x20
#define PTIP6 	0x40
#define PTIP7 	0x80

typedef union uDDRP		/*data direction register */
  {
  tU08	byte;
  struct
    {
    tU08 ddrp0	:1;		/*data direction bits (0:input;1:output) */
    tU08 ddrp1	:1;
    tU08 ddrp2	:1;
    tU08 ddrp3	:1;
    tU08 ddrp4	:1;
    tU08 ddrp5	:1;
    tU08 ddrp6	:1;
    tU08 ddrp7	:1;
    }bit;
  }tDDRP;

#define DDRP0	0x01	/*bit masks */
#define DDRP1	0x02
#define DDRP2	0x04
#define DDRP3	0x08
#define DDRP4	0x10
#define DDRP5	0x20
#define DDRP6	0x40
#define DDRP7	0x80

typedef union uRDRP		/*reduced drive register */
  {
  tU08	byte;
  struct
    {
    tU08 rdrp0	:1;		/*reduced drive bits (0:full;1:reduced) */
    tU08 rdrp1	:1;
    tU08 rdrp2	:1;
    tU08 rdrp3	:1;
    tU08 rdrp4	:1;
    tU08 rdrp5	:1;
    tU08 rdrp6	:1;
    tU08 rdrp7	:1;
    }bit;
  }tRDRP;

#define RDRP0	0x01	/*bit masks */
#define RDRP1	0x02
#define RDRP2	0x04
#define RDRP3	0x08
#define RDRP4	0x10
#define RDRP5	0x20
#define RDRP6	0x40
#define RDRP7	0x80

typedef union uPERP		/*pull-up/dn enable register */
  {
  tU08	byte;
  struct
    {
    tU08 perp0	:1;		/*pull-up/dn bits (1:enabled) */
    tU08 perp1	:1;
    tU08 perp2	:1;
    tU08 perp3	:1;
    tU08 perp4	:1;
    tU08 perp5	:1;
    tU08 perp6	:1;
    tU08 perp7	:1;
    }bit;
  }tPERP;

#define PERP0	0x01	/*bit masks */
#define PERP1	0x02
#define PERP2 	0x04
#define PERP3 	0x08
#define PERP4 	0x10
#define PERP5 	0x20
#define PERP6 	0x40
#define PERP7 	0x80

typedef union uPPSP		/*pull-up/dn polarity register */
  {
  tU08	byte;
  struct
    {
    tU08 ppsp0	:1;		/*pull-up/dn bits (0:pull-up;1:pull-dn) */
    tU08 ppsp1	:1;
    tU08 ppsp2	:1;
    tU08 ppsp3	:1;
    tU08 ppsp4	:1;
    tU08 ppsp5	:1;
    tU08 ppsp6	:1;
    tU08 ppsp7	:1;
    }bit;
  }tPPSP;

#define PPSP0	0x01	/*bit masks */
#define PPSP1	0x02
#define PPSP2 	0x04
#define PPSP3 	0x08
#define PPSP4 	0x10
#define PPSP5 	0x20
#define PPSP6 	0x40
#define PPSP7 	0x80

typedef union uPIEP		/*interrupt enable register */
  {
  tU08	byte;
  struct
    {
    tU08 piep0	:1;		/*interrupt source (1:enabled) */
    tU08 piep1	:1;
    tU08 piep2	:1;
    tU08 piep3	:1;
    tU08 piep4	:1;
    tU08 piep5	:1;
    tU08 piep6	:1;
    tU08 piep7	:1;
    }bit;
  }tPIEP;

#define PIEP0	0x01	/*bit masks */
#define PIEP1	0x02
#define PIEP2 	0x04
#define PIEP3 	0x08
#define PIEP4 	0x10
#define PIEP5 	0x20
#define PIEP6 	0x40
#define PIEP7 	0x80

typedef union uPIFP		/*wired-or mode register */
  {
  tU08	byte;
  struct
    {
    tU08 pifp0	:1;		/*wired-or bits (1:enabled) */
    tU08 pifp1	:1;
    tU08 pifp2	:1;
    tU08 pifp3	:1;
    tU08 pifp4	:1;
    tU08 pifp5	:1;
    tU08 pifp6	:1;
    tU08 pifp7	:1;
    }bit;
  }tPIFP;

#define PIFP0	0x01	/*bit masks */
#define PIFP1	0x02
#define PIFP2 	0x04
#define PIFP3 	0x08
#define PIFP4 	0x10
#define PIFP5 	0x20
#define PIFP6 	0x40
#define PIFP7 	0x80


/******************************  PORT H  **************************/

typedef union uPTH		/*i/o register */
  {
  tU08	byte;
  struct
    {
    tU08 pth0	:1;		/*i/o port pins */
    tU08 pth1	:1;
    tU08 pth2	:1;
    tU08 pth3	:1;
    tU08 pth4	:1;
    tU08 pth5	:1;
    tU08 pth6	:1;
    tU08 pth7	:1;
    }bit;
  }tPTH;

#define PTH0	0x01	/*bit masks */
#define PTH1	0x02
#define PTH2 	0x04
#define PTH3 	0x08
#define PTH4 	0x10
#define PTH5 	0x20
#define PTH6 	0x40
#define PTH7 	0x80

typedef union uPTIH		/*input register */
  {
  tU08	byte;
  struct
    {
    tU08 ptih0	:1;		/*i/o port pins */
    tU08 ptih1	:1;
    tU08 ptih2	:1;
    tU08 ptih3	:1;
    tU08 ptih4	:1;
    tU08 ptih5	:1;
    tU08 ptih6	:1;
    tU08 ptih7	:1;
    }bit;
  }tPTIH;

#define PTIH0	0x01	/*bit masks */
#define PTIH1	0x02
#define PTIH2 	0x04
#define PTIH3 	0x08
#define PTIH4 	0x10
#define PTIH5 	0x20
#define PTIH6 	0x40
#define PTIH7 	0x80

typedef union uDDRH		/*data direction register */
  {
  tU08	byte;
  struct
    {
    tU08 ddrh0	:1;		/*data direction bits (0:input;1:output) */
    tU08 ddrh1	:1;
    tU08 ddrh2	:1;
    tU08 ddrh3	:1;
    tU08 ddrh4	:1;
    tU08 ddrh5	:1;
    tU08 ddrh6	:1;
    tU08 ddrh7	:1;
    }bit;
  }tDDRH;

#define DDRH0	0x01	/*bit masks */
#define DDRH1	0x02
#define DDRH2	0x04
#define DDRH3	0x08
#define DDRH4	0x10
#define DDRH5	0x20
#define DDRH6	0x40
#define DDRH7	0x80

typedef union uRDRH		/*reduced drive register */
  {
  tU08	byte;
  struct
    {
    tU08 rdrh0	:1;		/*reduced drive bits (0:full;1:reduced) */
    tU08 rdrh1	:1;
    tU08 rdrh2	:1;
    tU08 rdrh3	:1;
    tU08 rdrh4	:1;
    tU08 rdrh5	:1;
    tU08 rdrh6	:1;
    tU08 rdrh7	:1;
    }bit;
  }tRDRH;

#define RDRH0	0x01	/*bit masks */
#define RDRH1	0x02
#define RDRH2	0x04
#define RDRH3	0x08
#define RDRH4	0x10
#define RDRH5	0x20
#define RDRH6	0x40
#define RDRH7	0x80

typedef union uPERH		/*pull-up/dn enable register */
  {
  tU08	byte;
  struct
    {
    tU08 perh0	:1;		/*pull-up/dn bits (1:enabled) */
    tU08 perh1	:1;
    tU08 perh2	:1;
    tU08 perh3	:1;
    tU08 perh4	:1;
    tU08 perh5	:1;
    tU08 perh6	:1;
    tU08 perh7	:1;
    }bit;
  }tPERH;

#define PERH0	0x01	/*bit masks */
#define PERH1	0x02
#define PERH2 	0x04
#define PERH3 	0x08
#define PERH4 	0x10
#define PERH5 	0x20
#define PERH6 	0x40
#define PERH7 	0x80

typedef union uPPSH		/*pull-up/dn polarity register */
  {
  tU08	byte;
  struct
    {
    tU08 ppsh0	:1;		/*pull-up/dn bits (0:pull-up;1:pull-dn) */
    tU08 ppsh1	:1;
    tU08 ppsh2	:1;
    tU08 ppsh3	:1;
    tU08 ppsh4	:1;
    tU08 ppsh5	:1;
    tU08 ppsh6	:1;
    tU08 ppsh7	:1;
    }bit;
  }tPPSH;

#define PPSH0	0x01	/*bit masks */
#define PPSH1	0x02
#define PPSH2 	0x04
#define PPSH3 	0x08
#define PPSH4 	0x10
#define PPSH5 	0x20
#define PPSH6 	0x40
#define PPSH7 	0x80

typedef union uPIEH		/*interrupt enable register */
  {
  tU08	byte;
  struct
    {
    tU08 pieh0	:1;		/*interrupt source (1:enabled) */
    tU08 pieh1	:1;
    tU08 pieh2	:1;
    tU08 pieh3	:1;
    tU08 pieh4	:1;
    tU08 pieh5	:1;
    tU08 pieh6	:1;
    tU08 pieh7	:1;
    }bit;
  }tPIEH;

#define PIEH0	0x01	/*bit masks */
#define PIEH1	0x02
#define PIEH2 	0x04
#define PIEH3 	0x08
#define PIEH4 	0x10
#define PIEH5 	0x20
#define PIEH6 	0x40
#define PIEH7 	0x80

typedef union uPIFH		/*wired-or mode register */
  {
  tU08	byte;
  struct
    {
    tU08 pifh0	:1;		/*wired-or bits (1:enabled) */
    tU08 pifh1	:1;
    tU08 pifh2	:1;
    tU08 pifh3	:1;
    tU08 pifh4	:1;
    tU08 pifh5	:1;
    tU08 pifh6	:1;
    tU08 pifh7	:1;
    }bit;
  }tPIFH;