s12_bdlc.h

PWM Generation Using HCS12 Timer Channels

/*****************************************************************************/
/*                                             COPYRIGHT (c) MOTOROLA 2002   */
/*                                                                           */
/* File Name        :  $RCSfile: s12_bdlc.h,v $  						     */
/*                                                                           */
/* Current Revision :  $Revision: 1.2 $									     */
/*                                                                           */
/* PURPOSE: header file for HCS12 J1850 byte data link controller (BDLC)	 */
/*			register block	   			 		 							 */
/*                                                                           */
/*  ***********************************************************************  */
/*  *  THIS CODE IS ONLY INTENDED AS AN EXAMPLE OF CODE FOR THE           *  */
/*  *  METROWERKS COMPILER AND THE STAR12 EVB AND HAS ONLY BEEN GIVEN A   *  */
/*  *  MIMIMUM LEVEL OF TEST. IT IS PROVIDED 'AS SEEN' WITH NO GUARANTEES *  */
/*  *  AND NO PROMISE OF SUPPORT.                                         *  */
/*  ***********************************************************************  */
/*                                                                           */
/*                                                                           */
/* DESCRIPTION:  Defines the BDLC register block as a datastructure          */
/*               of type tBDLC.                                              */
/* 																		     */
/* BDLC module base address (out of reset) -                                 */
/*                                                                           */
/* S12DP256      : 0x00E8                                                    */
/*																			 */
/* The datastructure compiled can be determined by the #define's S12DP256,   */
/* S12xxx, etc. These definitions can be found in "s12_common.h".            */
/* The MCU id can be #defined in a "target.h" header file or included as a   */
/* complier command line argument as -DS12DP256.                             */
/* Currently only S12DP256 is supported.									 */
/*																			 */
/* Multiple register descriptions are used when a differing bit structure    */
/* exists between parts. In the case of additional bit definitions within    */
/* the same register, then only the full register description is used.       */
/*                                                                           */
/*                                                                           */
/* AUTHOR: R32151            LOCATION: SPSEKB      LAST EDIT DATE: 14/03/02  */
/*                                                                           */
/* UPDATE HISTORY                                                            */
/* REV  AUTHOR       DATE       DESCRIPTION OF CHANGE                        */
/* ---  ------      --------    ---------------------                        */
/* 1.00	r32151  	10/05/00                                                 */
/* 1.01	r32151  	25/05/00  	- corrected definition of TMIFR1 bit         */
/*                                (was incorrectly TMIFR0)                   */
/* 1.02 r32151  	10/5/00 	- changed definition of idle bit to bidle to */
/*                                avoid contention with SCI idle bit		 */
/* 1.1  r32151      11/03/02	- Added disclaimer and reformated file info. */
/*                              - Modified revision numbering to match RCS   */
/* 1.2  r32151      14/03/02	- Declared all registers volatile 	 		 */
/*                              - changed tU08 declarations in structure to  */
/*                                tREG08 to standardise all accesses as      */
/*                                using .bit or .byte format                 */
/*                                                                           */
/*===========================================================================*/
/* Motorola reserves the right to make changes without further notice to any */
/* product herein to improve reliability, function, or design. Motorola does */
/* not assume any  liability arising  out  of the  application or use of any */
/* product,  circuit, or software described herein;  neither  does it convey */
/* any license under its patent rights  nor the  rights of others.  Motorola */
/* products are not designed, intended,  or authorized for use as components */
/* in  systems  intended  for  surgical  implant  into  the  body, or  other */
/* applications intended to support life, or  for any  other application  in */
/* which the failure of the Motorola product  could create a situation where */
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/* affiliates,  and distributors harmless against all claims costs, damages, */
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/* indirectly,  any claim of personal injury  or death  associated with such */
/* unintended or unauthorized use, even if such claim alleges that  Motorola */
/* was negligent regarding the  design  or manufacture of the part. Motorola */
/* and the Motorola logo* are registered trademarks of Motorola Ltd.         */
/*****************************************************************************/

#ifndef S12_BDLC_H			/*prevent duplicated includes */
#define S12_BDLC_H

#ifndef S12_COMMON_H		/*prevent duplicated includes */
#include "s12_common.h"
#endif

typedef union uDLCBCR1
  {
  tU08	byte;
  struct
    {
    tU08 wcm	:1;		/*wait clock mode select	*/
    tU08 ie		:1;		/*interrupt enable */
    tU08 		:4;		/*not used */
    tU08 clks	:1;		/*clock select */
    tU08 imsg	:1;		/*ignore message */
    }bit;
  }tDLCBCR1;

#define WCM		0x01	/*bit masks	*/
#define IE		0x02
#define CLKS	0x40
#define IMSG	0x80

typedef union uDLCBSVR
  {
  tU08	byte;
  struct
    {
    tU08 		:2;		/*not used */
    tU08 i0		:1;		/*interrupt state vector bits */
    tU08 i1		:1;
    tU08 i2		:1;
    tU08 i3		:1;
    tU08 		:2;		/*not used */
    }bit;
  }tDLCBSVR;

#define I0		0x04	/*bit masks	*/
#define I1		0x08
#define I2		0x10
#define I3		0x20

typedef union uDLCBCR2
  {
  tU08	byte;
  struct
    {
    tU08 tmifr0	:1;		/*transmit in-frame response control 0 */
    tU08 tmifr1	:1;		/*transmit in-frame response control 1 */
    tU08 tsifr	:1;		/*transmit single byte IFR with no CRC */
    tU08 teod	:1;		/*transmit end of data */
    tU08 nbfs	:1;		/*normalization bit format select */
    tU08 rx4xe	:1;		/*receive 4x enable	*/
    tU08 dloop	:1;		/*digital loop back mode */
    tU08 smrst	:1;		/*state machine reset */
    }bit;
  }tDLCBCR2;

#define TMIFR0	0x01	/*bit masks	*/
#define TMIFR1	0x02
#define TSIFR 	0x04
#define TEOD	0x08
#define NBFS	0x10
#define RX4XE	0x20
#define DLOOP	0x40
#define SMRST	0x80

typedef union uDLCBARD
  {
  tU08	byte;
  struct
    {
    tU08 bo		:4;		/*analog round trip offset*/
    tU08 		:2;		/*not used*/
    tU08 rxpol	:1;		/*receive pin polarity */
    tU08 		:1;		/*not used*/
    }bit;
  }tDLCBARD;

#define B0		0x01	/*bit masks	*/
#define B1		0x02
#define B2		0x04
#define B3		0x08
#define RXPOL	0x40

typedef union uDLCBRSR
  {
  tU08	byte;
  struct
    {
    tU08 r		:6;		/*rate select bits	*/
    tU08 		:2;		/*not used */
    }bit;
  }tDLCBRSR;

#define R0		0x01	/*bit masks	*/
#define R1		0x02
#define R2		0x04
#define R3		0x08
#define R4		0x10
#define R5		0x20

typedef union uDLCSCR
  {
  tU08	byte;
  struct
    {
    tU08 		:4;		/*not used*/
    tU08 bdlce	:1;		/*bdlc enable */
    tU08 		:3;		/*not used*/
    }bit;
  }tDLCSCR;

#define BDLCE	0x10	/*bit masks	*/

typedef union uDLCBSTAT
  {
  tU08	byte;
  struct
    {
    tU08 bidle	:1;		/*idle status */
    tU08 		:7;		/*not used*/
    }bit;
  }tDLCBSTAT;
						/*NOTE: idle bit declared as bidle to avoid */
						/*      contention with SCI idle bit */

#define BIDLE	0x01	/*bit masks	*/

typedef struct						/*bdlc datastructure	*/
  {
  volatile tDLCBCR1		dlcbcr1;	/*bdlc control register 1 */
  volatile tDLCBSVR		dlcbsvr;	/*bdlc state vector register */
  volatile tDLCBCR2		dlcbcr2;	/*bdlc control register 2 */
  volatile tREG08		dlcbdr;		/*bdlc data register */
  volatile tDLCBARD		dlcbard;	/*bdlc analog round trip delay register */
  volatile tDLCBRSR		dlcbrsr;	/*bdlc rate select register */
  volatile tDLCSCR		dlcscr;		/*bdlc control register */
  volatile tDLCBSTAT	dlcbstat;	/*bdlc status register */
  }tBDLC;


#endif /*S12_BDLC_H */