s12_fectl.h

PWM Generation Using HCS12 Timer Channels

/******************************************************************************
													Copyright (c) Motorola 2000
File Name		 :	$RCSfile: s12_fectl.h,v $		
	
Engineer		 :	$Author: r27624 $

Location		 :	EKB

Date Created	 :	09/01/01

Current Revision :	$Revision: 1.1 $

Notes	:					

*******************************************************************************
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#ifndef FECTL_H
#define FECTL_H

#define UINT8 tU08
#define UINT16 tU16

/************************* System Include Files ******************************/


/************************* Project Include Files *****************************/

/************************* typedefs ******************************************/


/************************* Extern Variables **********************************/


/************************* #Defines ******************************************/
#define FDIV8	0x40	/*bit masks	*/
#define FDIVLD	0x80

#define SEC00	0x01	/*bit masks	*/
#define SEC01	0x02
#define NV2		0x04
#define NV3		0x08
#define NV4		0x10
#define NV5 	0x20
#define NV6		0x40
#define KEYEN	0x80

#define BKSEL0	0x01	/*bit masks	*/
#define BKSEL1	0x02
#define BKSEL	0x03	/*bank select mask */
#define KEYACC	0x20	
#define CCIE	0x40	
#define CCBIE	0x80

#define FPLS0	0x01	/*bit masks	*/
#define FPLS1	0x02
#define FPLS	0x03	/*fpls block size mask */
#define FPLDIS	0x04	
#define FPHS0	0x08	
#define FPHS1	0x10
#define FPHS	0x18	/*fphs block size mask */
#define FPHDIS	0x20	
#define FOPEN	0x80

#define BLANK	0x04	/*bit masks	*/
#define ACCERR	0x10
#define PVIOL 	0x20
#define CCIF	0x40
#define CBEIF	0x80

#define MASS	0x01	/*bit masks	*/
#define ERVER	0x04
#define PROG	0x20
#define ERASE	0x40

/************************* Macros ********************************************/

   /* Macro that generates the FLASH clock precaler as per data book. 
      If the crystal frequency is above 12.8MHz then the FDIV bit must 
      be set, this divides the OSCCLK frequency by 8 before the prescaler. */

#if (OSCCLK_FREQ_KHZ > 12800)  
   /* This macro calculates the prescaler, but also implements the FDIV8 bit */
#if ((OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200)) % (1600 * BUSCLK_FREQ_KHZ) == 0)
#define FCLK_PRESCALER ((OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200) / (1600 * BUSCLK_FREQ_KHZ)) + FDIV8 - 1)
#else
#define FCLK_PRESCALER ((OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200) / (1600 * BUSCLK_FREQ_KHZ)) + FDIV8)
#endif /* OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200) % (1600 * BUSCLK_FREQ_KHZ) == 0 */
   /* Make sure FCLK is within specified range. */
#define FCLK_FREQ_KHZ (OSCCLK_FREQ_KHZ / (8 * (1 + FCLK_PRESCALER - FDIV8))) 
#if ((FCLK_FREQ_KHZ < 150) || (FCLK_FREQ_KHZ > 200) || (FCLK_PRESCALER > 0x7F))
#error FLASH prescaler or clock out of range.
#endif /* Incorrect FCLK frequency. */

#else
   /* This macro calculates the prescaler. */
#if ((OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200)) % (200 * BUSCLK_FREQ_KHZ) == 0)
#define FCLK_PRESCALER ((OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200) / (200 * BUSCLK_FREQ_KHZ)) - 1)
#else
#define FCLK_PRESCALER (OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200) / (200 * BUSCLK_FREQ_KHZ))
#endif /* OSCCLK_FREQ_KHZ * (BUSCLK_FREQ_KHZ + 200) % (200 * BUSCLK_FREQ_KHZ) == 0 */ 
   /* Make sure FCLK is within specified range. */
#define FCLK_FREQ_KHZ (OSCCLK_FREQ_KHZ / (1 + FCLK_PRESCALER)) 
#if ((FCLK_FREQ_KHZ < 150) || (FCLK_FREQ_KHZ > 200) || (FCLK_PRESCALER > 0x3F))
#error FLASH prescaler or clock out of range.
#endif /* Incorrect FCLK frequency. */
#endif /* OSCCLK_FREQ_KHZ > 12800 */


/************************* Prototypes ****************************************/
void  ConfigFCLKDIV(void);
UINT8 ProgFlash(UINT16*, UINT16*, UINT16);
UINT8 EraseFlash(UINT16*);

#pragma CODE_SEG DEFAULT

#endif	/* End of Header file !defined	*/