📄 s12_register.h
字号:
/*****************************************************************************/
/* COPYRIGHT (c) MOTOROLA 2002 */
/* */
/* File Name : $RCSfile: s12_register.h,v $ */
/* */
/* Current Revision : $Revision: 1.5 $ */
/* */
/* PURPOSE: header file for HCS12 register block */
/* */
/* *********************************************************************** */
/* * THIS CODE IS ONLY INTENDED AS AN EXAMPLE OF CODE FOR THE * */
/* * METROWERKS COMPILER AND THE HCS12 EVB AND HAS ONLY BEEN GIVEN A * */
/* * MIMIMUM LEVEL OF TEST. IT IS PROVIDED 'AS SEEN' WITH NO GUARANTEES * */
/* * AND NO PROMISE OF SUPPORT. * */
/* *********************************************************************** */
/* */
/* */
/* DESCRIPTION: standard definitions for HCS12 core registers block */
/* Defines the external bus ports (A, B & E), system registers and bdm */
/* registers as a datastructure of type tREGISTER. */
/* */
/* Datastructure base address (out of reset) - */
/* */
/* HCS12 0x0000 */
/* */
/* The datastructure compiled can be determined by the #define's S12DP256, */
/* S12xxx, etc. These definitions can be found in "s12_common.h". */
/* The MCU id can be #defined in a "target.h" header file or included as a */
/* complier command line argument e.g: -DS12DP256. */
/* This file provides support for core versions up to v1.5. Core v1.5 support*/
/* can be enabled by defining COREV1_5. */
/* */
/* Multiple register descriptions are used when a differing bit structure */
/* exists between parts. In the case of additional bit definitions within */
/* the same register, then only the full register description is used. */
/* */
/* */
/* AUTHOR: r32151/r58711 LOCATION: SPSEKB LAST EDIT DATE: 13.09.02 */
/* */
/* UPDATE HISTORY */
/* REV AUTHOR DATE DESCRIPTION OF CHANGE */
/* --- ------ -------- --------------------- */
/* 1.00 r32151 28/4/00 - initial coding */
/* 1.01 r32151 09/05/00 - corrected missing def for partid, */
/* - fixed typos in def of itest, mtst0 & mtst1.*/
/* - Added some bits detail to partid comments. */
/* 1.02 r32151 10/05/00 - added missing 't' to tPARTID */
/* - Changed #include <s12_common.h> */
/* to #include "s12_common.h" */
/* - changed bit/mask names on Ports A, B */
/* and E consistant with PIM ports */
/* 1.03 r32151 25/05/00 - corrected typo in typedef of uDDRA1.0 */
/* 1.04 r32151 25/07/01 - changed CPU id MCSDP256 to S12DP256 */
/* - Added disclaimer and reformated file info. */
/* 1.1 r32151 11/03/02 - Updated file info. */
/* - Modified revision numbering to match RCS */
/* 1.2 r32151 14/03/02 - made all registers volatile */
/* 2.0 r58711 12/09/02 - modified map for v1.5 core (C32) */
/* 2.1 r58711 13/09/02 - made all reserved areas volatile */
/* */
/*===========================================================================*/
/* Motorola reserves the right to make changes without further notice to any */
/* product herein to improve reliability, function, or design. Motorola does */
/* not assume any liability arising out of the application or use of any */
/* product, circuit, or software described herein; neither does it convey */
/* any license under its patent rights nor the rights of others. Motorola */
/* products are not designed, intended, or authorized for use as components */
/* in systems intended for surgical implant into the body, or other */
/* applications intended to support life, or for any other application in */
/* which the failure of the Motorola product could create a situation where */
/* personal injury or death may occur. Should Buyer purchase or use Motorola */
/* products for any such intended or unauthorized application, Buyer shall */
/* indemnify and hold Motorola and its officers, employees, subsidiaries, */
/* affiliates, and distributors harmless against all claims costs, damages, */
/* and expenses, and reasonable attorney fees arising out of, directly or */
/* indirectly, any claim of personal injury or death associated with such */
/* unintended or unauthorized use, even if such claim alleges that Motorola */
/* was negligent regarding the design or manufacture of the part. Motorola */
/* and the Motorola logo* are registered trademarks of Motorola Ltd. */
/*****************************************************************************/
#ifndef S12_REGISTER_H /*prevent duplicated includes */
#define S12_REGISTER_H
#ifndef S12_COMMON_H /*prevent duplicated includes */
#include "S12_common.h"
#endif
typedef union uPORTA
{
tU08 byte;
struct
{
tU08 pta0 :1; /*i/o port pins */
tU08 pta1 :1;
tU08 pta2 :1;
tU08 pta3 :1;
tU08 pta4 :1;
tU08 pta5 :1;
tU08 pta6 :1;
tU08 pta7 :1;
}bit;
}tPORTA;
#define PTA0 0x01 /*bit masks */
#define PTA1 0x02
#define PTA2 0x04
#define PTA3 0x08
#define PTA4 0x10
#define PTA5 0x20
#define PTA6 0x40
#define PTA7 0x80
typedef union uPORTB
{
tU08 byte;
struct
{
tU08 ptb0 :1; /*i/o port pins */
tU08 ptb1 :1;
tU08 ptb2 :1;
tU08 ptb3 :1;
tU08 ptb4 :1;
tU08 ptb5 :1;
tU08 ptb6 :1;
tU08 ptb7 :1;
}bit;
}tPORTB;
#define PTB0 0x01 /*bit masks */
#define PTB1 0x02
#define PTB2 0x04
#define PTB3 0x08
#define PTB4 0x10
#define PTB5 0x20
#define PTB6 0x40
#define PTB7 0x80
typedef union uDDRA
{
tU08 byte;
struct
{
tU08 ddra0 :1; /*data direction bits (0:input;1:output) */
tU08 ddra1 :1;
tU08 ddra2 :1;
tU08 ddra3 :1;
tU08 ddra4 :1;
tU08 ddra5 :1;
tU08 ddra6 :1;
tU08 ddra7 :1;
}bit;
}tDDRA;
#define DDRA0 0x01 /*bit masks */
#define DDRA1 0x02
#define DDRA2 0x04
#define DDRA3 0x08
#define DDRA4 0x10
#define DDRA5 0x20
#define DDRA6 0x40
#define DDRA7 0x80
typedef union uDDRB
{
tU08 byte;
struct
{
tU08 ddrb0 :1; /*data direction bits (0:input;1:output) */
tU08 ddrb1 :1;
tU08 ddrb2 :1;
tU08 ddrb3 :1;
tU08 ddrb4 :1;
tU08 ddrb5 :1;
tU08 ddrb6 :1;
tU08 ddrb7 :1;
}bit;
}tDDRB;
#define DDRB0 0x01 /*bit masks */
#define DDRB1 0x02
#define DDRB2 0x04
#define DDRB3 0x08
#define DDRB4 0x10
#define DDRB5 0x20
#define DDRB6 0x40
#define DDRB7 0x80
typedef union uPORTE
{
tU08 byte;
struct
{
tU08 pte0 :1; /*i/o port pins */
tU08 pte1 :1;
tU08 pte2 :1;
tU08 pte3 :1;
tU08 pte4 :1;
tU08 pte5 :1;
tU08 pte6 :1;
tU08 pte7 :1;
}bit;
}tPORTE;
#define PTE0 0x01 /*bit masks */
#define PTE1 0x02
#define PTE2 0x04
#define PTE3 0x08
#define PTE4 0x10
#define PTE5 0x20
#define PTE6 0x40
#define PTE7 0x80
typedef union uDDRE
{
tU08 byte;
struct
{
tU08 :2;
tU08 ddre2 :1; /*data direction bits (0:input;1:output) */
tU08 ddre3 :1;
tU08 ddre4 :1;
tU08 ddre5 :1;
tU08 ddre6 :1;
tU08 ddre7 :1;
}bit;
}tDDRE;
#define DDRE2 0x04 /*bit masks */
#define DDRE3 0x08
#define DDRE4 0x10
#define DDRE5 0x20
#define DDRE6 0x40
#define DDRE7 0x80
typedef union uPEAR
{
tU08 byte;
struct
{
tU08 :2;
tU08 rdwe :1; /*read/write enable */
tU08 lstre :1; /*low strobe enable */
tU08 neclk :1; /*no external eclk */
tU08 pipoe :1; /*pipe status signal output enable */
tU08 :1;
tU08 noacce :1; /*cpu no access output enable */
}bit;
}tPEAR;
#define RDWE 0x04 /*bit masks */
#define LSTRE 0x08
#define NECLK 0x10
#define PIPOE 0x20
#define NOACCE 0x80
typedef union uMODE
{
tU08 byte;
struct
{
tU08 eme :1; /*emulate port E */
tU08 emk :1; /*emulate port K */
tU08 :1;
tU08 ivis :1; /*internal visibility */
tU08 :1;
tU08 moda :1; /*mode select bits */
tU08 modb :1;
tU08 modc :1;
}bit;
}tMODE;
#define EME 0x01 /*bit masks */
#define EMK 0x02
#define IVIS 0x08
#define MODA 0x20
#define MODB 0x40
#define MODC 0x80
typedef union uPUCR
{
tU08 byte;
struct
{
tU08 pupae :1; /*pull-up port A enable */
tU08 pupbe :1; /*pull-up port B enable */
tU08 :2;
tU08 pupee :1; /*pull-up port E enable */
tU08 :2;
tU08 pupke :1; /*pull-up port K enable */
}bit;
}tPUCR;
#define PUPAE 0x01 /*bit mask */
#define PUPBE 0x02
#define PUPEE 0x10
#define PUPKE 0x40
typedef union uRDRIV
{
tU08 byte;
struct
{
tU08 rdpa :1; /*reduced drive port A */
tU08 rdpb :1; /*reduced drive port B */
tU08 :2;
tU08 rdpe :1; /*reduced drive port E */
tU08 :2;
tU08 rdpk :1; /*reduced drive port K */
}bit;
}tRDRIV;
#define RDPA 0x01 /*bit mask */
#define RDPB 0x02
#define RDPE 0x10
#define RDPK 0x80
typedef union uEBICTL
{
tU08 byte;
struct
{
tU08 estr :1; /*e-clock free running or bus control signal */
tU08 :7; /*not used */
}bit;
}tEBICTL;
#define ESTR 0x01 /*bit mask */
typedef union uINITRM
{
tU08 byte;
struct
{
tU08 :1; /*RAM hi or low alignment within 16K page */
tU08 :2; /*not used */
tU08 ram :5; /*internal ram map position */
}bit;
}tINITRM;
#define RAMHAL 0x01 /*bit masks */
#define RAM11 0x08
#define RAM12 0x10
#define RAM13 0x20
#define RAM14 0x40
#define RAM15 0x80
typedef union uINITRG
{
tU08 byte;
struct
{
tU08 :3; /*not used */
tU08 reg :5; /*internal register map position */
}bit;
}tINITRG;
#define REG11 0x08 /*bit masks */
#define REG12 0x10
#define REG13 0x20
#define REG14 0x40
#define REG15 0x80
typedef union uINITEE
{
tU08 byte;
struct
{
tU08 eeon :1; /*internal eeprom on */
tU08 :3; /*not used */
tU08 ee :4; /*internal eeprom map position */
}bit;
}tINITEE;
#define EEON 0x01 /*bit masks */
#define EE12 0x10
#define EE13 0x20
#define EE14 0x40
#define EE15 0x80
typedef union uMISC
{
tU08 byte;
struct
{
tU08 romon :1; /*enable flash */
tU08 romhm :1; /*flash only in second half of map */
tU08 exstr :2; /*external access clock stretch */
tU08 :4; /*not used */
}bit;
}tMISC;
#define ROMON 0x01 /*bit masks */
#define ROMHM 0x02
#define EXSTR0 0x04
#define EXSTR1 0x08
typedef union uMTST /*memory test registers */
{
tU08 byte;
struct
{
tU08 bit :8;
}bit;
}tMTST;
typedef union uITCR
{
tU08 byte;
struct
{
tU08 adr0 :1; /*interrupt test control */
tU08 adr1 :1;
tU08 adr2 :1;
tU08 adr3 :1;
tU08 wrint :1;
tU08 :3; /*not used */
}bit;
}tITCR;
#define ADR0 0x01 /*bit masks */
#define ADR1 0x02
#define ADR2 0x04
#define ADR3 0x08
#define WRINT 0x10
typedef union uITEST
{
tU08 byte;
struct
{
tU08 int0 :1; /*interrupt test register */
tU08 int2 :1;
tU08 int4 :1;
tU08 int6 :1;
tU08 int8 :1;
tU08 inta :1;
tU08 intc :1;
tU08 inte :1;
}bit;
}tITEST;
#define INT0 0x01 /*bit masks */
#define INT2 0x02
#define INT3 0x04
#define INT6 0x08
#define INT8 0x10
#define INTA 0x20
#define INTC 0x40
#define INTE 0x80
typedef union uVREG
{
tU08 byte;
struct
{
tU08 lvif :1; /*vreg control register */
tU08 lvie :1;
tU08 lvds :1;
tU08 :5; /*unused */
}bit;
}tVREG;
#define LVIF 0x01 /*bit masks */
#define LVIE 0x02
#define LVDS 0x04
typedef union uPARTID /* bits 1:3 minor mask revs */
{ /* bits 4:7 major mask revs - inc fab x'fer */
tU16 word; /* bits 8:11 minor family id */
struct /* bits 12:15 major family id */
{
tU08 partidh;
tU08 partidl;
}byte;
}tPARTID;
typedef union uMEMSIZ0
{
tU08 byte;
struct
{
tU08 ram_sw :3;
tU08 :1;
tU08 eep_sw :2;
tU08 :1;
tU08 reg_sw :1;
}bit;
}tMEMSIZ0;
#define RAM_SW0 0x01 /*bit masks */
#define RAM_SW1 0x02
#define RAM_SW2 0x04
#define EEP_SW0 0x10
#define EEP_SW1 0x20
#define REG_SW0 0x80
typedef union uMEMSIZ1
{
tU08 byte;
struct
{
tU08 pag_sw :2;
tU08 :4;
tU08 rom_sw :2;
}bit;
}tMEMSIZ1;
#define PAG_SW0 0x01 /*bit masks */
#define PAG_SW1 0x02
#define ROM_SW0 0x40
#define ROM_SW1 0x80
typedef union uINTCR
{
tU08 byte;
struct
{
tU08 :6; /*not used */
tU08 irqen :1; /*external irq enable */
tU08 irqe :1; /*irq select edge sensitive only */
}bit;
}tINTCR;
#define IRQEN 0x40 /*bit masks */
#define IRQE 0x80
typedef union uHPRIO
{
tU08 byte;
struct
{
tU08 :1; /*not used */
tU08 psel1 :1; /*highest priority interrupt select bits */
tU08 psel2 :1;
tU08 psel3 :1;
tU08 psel4 :1;
tU08 psel5 :1;
tU08 psel6 :1;
tU08 psel7 :1;
}bit;
}tHPRIO;
#define PSEL1 0x02 /*bit masks */
#define PSEL2 0x04
#define PSEL3 0x08
#define PSEL4 0x10
#define PSEL5 0x20
#define PSEL6 0x40
#define PSEL7 0x80
typedef union uBKPCT0
{
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -