s12_crg.h

PWM Generation Using HCS12 Timer Channels

/*****************************************************************************/
/*                                             COPYRIGHT (c) MOTOROLA 2002   */
/*                                                                           */
/* File Name          :    $RCSfile: s12_crg.h,v $                           */
/*                                                                           */
/* Current Revision :      $Revision: 1.2 $									 */
/*                                                                           */
/* PURPOSE: header file for HCS12 CRG block     					 		 */
/*                                                                           */
/*  ***********************************************************************  */
/*  *  THIS CODE IS ONLY INTENDED AS AN EXAMPLE OF CODE FOR THE           *  */
/*  *  METROWERKS COMPILER AND THE STAR12 EVB AND HAS ONLY BEEN GIVEN A   *  */
/*  *  MIMIMUM LEVEL OF TEST. IT IS PROVIDED 'AS SEEN' WITH NO GUARANTEES *  */
/*  *  AND NO PROMISE OF SUPPORT.                                         *  */
/*  ***********************************************************************  */
/*                                                                           */
/* DESCRIPTION: Defines the Clocks and Reset Generator (inc pll) block as a  */
/* datastructure of type tCRG.                           					 */
/* 																		     */
/* CRG Datastructure base address (out of reset) -                           */
/*                                                                           */
/* S12DP256      : 0x0034                                                    */
/*                                                                           */
/* The datastructure compiled can be determined by the #define's S12DP256,   */
/* S12xxx, etc. These definitions can be found in "s12_common.h".            */
/* The MCU id can be #defined in a "target.h" header file or included as a   */
/* complier command line argument as -DS12DP256.                             */
/* Currently only S12DP256 is supported.									 */
/*																			 */
/* Multiple register descriptions are used when a differing bit structure    */
/* exists between parts. In the case of additional bit definitions within    */
/* the same register, then only the full register description is used.       */
/*                                                                           */
/*                                                                           */
/* AUTHOR: r32151               LOCATION: SPSEKB   LAST EDIT DATE: 14.03.02  */
/*                                                                           */
/* UPDATE HISTORY                                                            */
/* REV  AUTHOR       DATE       DESCRIPTION OF CHANGE                        */
/* ---  ------      --------    ---------------------                        */
/* 1.00	r32151  	5/5/00		- Initial coding                             */
/* 1.01  r32151  	10/5/00 	- Changed #include <s12_common.h> 		     */
/* 							      to #include "s12_common.h"			     */
/* 1.02 r32151      27/11/00 	- Changed ARMCOP declaration to 'volatile'   */   
/* 1.03 r32151      26/07/01	- UPDATED TO SUPPORT MASK 0K79X              */ 
/*                              - changed CPU id MCSDP256 to S12DP256.       */
/*                              - Added new PCE & PRE bits to uPLLCTL.       */
/*                              - Added disclaimer and reformated file info. */
/* 1.1  r32151  	11/03/02	- Corrected prof and PROF to porf and PORF   */	
/*                              - Modified revision numbering to match RCS   */
/* 1.2  r32151      14/03/02	- Declared all registers volatile 	 	     */
/*                              - changed tU08 declarations in structure to  */
/*                                tREG08 to standardise all accesses as      */
/*                                using .bit or .byte format                 */
/*                                                                           */
/*===========================================================================*/
/* Motorola reserves the right to make changes without further notice to any */
/* product herein to improve reliability, function, or design. Motorola does */
/* not assume any  liability arising  out  of the  application or use of any */
/* product,  circuit, or software described herein;  neither  does it convey */
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/* in  systems  intended  for  surgical  implant  into  the  body, or  other */
/* applications intended to support life, or  for any  other application  in */
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/* indirectly,  any claim of personal injury  or death  associated with such */
/* unintended or unauthorized use, even if such claim alleges that  Motorola */
/* was negligent regarding the  design  or manufacture of the part. Motorola */
/* and the Motorola logo* are registered trademarks of Motorola Ltd.         */
/*****************************************************************************/

#ifndef S12_CRG_H			/*prevent duplicated includes */
#define S12_CRG_H

#ifndef S12_COMMON_H		/*prevent duplicated includes */
#include "s12_common.h"
#endif		   

typedef union uSYNR
  {
  tU08	byte;
  struct
    {
    tU08 syn	:6;		/*synthesizer bits, controls multiplication factor of PLL */
    tU08		:2;		/*not used */
    }bit;
  }tSYNR;

#define SYN0	0x01	/*bit masks	*/
#define SYN1	0x02
#define SYN2	0x04
#define SYN3	0x08
#define SYN4	0x10
#define SYN5	0x20

typedef union uREFDV
  {
  tU08	byte;
  struct
    {
    tU08 refdv	:4;		/*allows finer granularity for pll ref freq	*/
    tU08		:4;		/*not used */
    }bit;
  }tREFDV;

#define REFDV0	0x01	/*bit masks	*/
#define REFDV1	0x02
#define REFDV2	0x04
#define REFDV3	0x08


typedef union uCRGFLG
  {
  tU08	byte;
  struct
    {
    tU08 scm	:1;		/*self clock mode ststus (1: limp-home clock active) */
    tU08 scmif	:1;		/*self clock mode interrupt flag */
	tU08 track	:1;		/*track status*/
    tU08 lock	:1;		/*lock status */
    tU08 lockif	:1;		/*lock interrupt flag */
    tU08		:1;		/*not used */
	tU08 porf	:1;		/*power on reset flag */
	tU08 rtif	:1;		/*real time interrupt flag */
    }bit;
  }tCRGFLG;

#define SCM		0x01	/*bit masks	*/
#define SCMIF	0x02
#define TRACK	0x04	
#define LOCK	0x08	
#define LOCKIF	0x10	
#define PORF	0x40	
#define RTIF	0x80

typedef union uCRGINT
  {
  tU08	byte;
  struct
    {
	tU08 		:1;		/*not used*/
    tU08 scmIe	:1;		/*self clock mode interrupt enable */
	tU08 		:2;		/*not used*/
    tU08 lockie	:1;		/*lock interrupt enable */
    tU08		:2;		/*not used */
	tU08 rtie	:1;		/*real time interrupt enable */
    }bit;
  }tCRGINT;

#define SCMIE	0x02	/*bit masks	*/
#define LOCKIF	0x10	
#define RTIF	0x80


typedef union uCLKSEL
  {
  tU08	byte;
  struct
    {
    tU08 copwai	:1;		/*not used */
    tU08 rtiwai	:1;		/*module clock select */
    tU08 cwai	:1;		/*not used */
    tU08 pllwai	:1;		/*bus clock select slow	*/
    tU08 roawai	:1;		/*bus clock select pll */
    tU08 syswai	:1;		/*system clock stoped in wait mode */
    tU08 pstp	:1;		/*pseudo stop mode enable */
    tU08 pllsel	:1;		/*pll select */
    }bit;
  }tCLKSEL;

#define COPWAI	  0x01		/*bit masks */
#define RTIWAI	  0x02		
#define CWAI	  0x04		
#define PLLWAI	  0x08		
#define ROAWAI	  0x10		
#define SYSWAI	  0x20		
#define PSTP	  0x40		
#define PLLSEL	  0x80		

typedef union uPLLCTL
  {
  tU08	byte;
  struct
    {
    tU08 scme	:1;		/*self clock mode enable */
	tU08 pce	:1;		/*pseudo stop COP enable */
    tU08 pre	:1;		/*pseudo stop RTI enable */
    tU08		:1;		/*not used */
    tU08 acq	:1;		/*not in acquisition */
    tU08 aut	:1;		/*automatic bandwidth control */
    tU08 pllon	:1;		/*phase lock loop on */
    tU08 cme	:1;		/*crystal monitor enable */
    }bit;
  }tPLLCTL;

/****

The bitfield aut was used instead of auto, as auto is a C keyword and may be
problematic to some compilers.

****/

#define SCME	0x01	/*bit masks	*/
#define PCE		0x02
#define PRE		0x04
#define ACQ		0x10
#define AUTO	0x20
#define PLLON	0x40
#define CME		0x80

typedef union uCOPCTL
  {			  
  tU08	byte;
  struct
    {
    tU08 cr		:3;		/*cop timer rate select */
    tU08		:4;		/*not used */
    tU08 wcop	:1;		/*window cop enable */
    }bit;
  }tCOPCTL;

#define CR0		0x01	/*bit masks	*/
#define CR1		0x02
#define CR2		0x04
#define WCOP	0x80

typedef union uFORBYP		
  {
  tU08	byte;
  struct
    {
    tU08		:1;		/*not used */
    tU08 fcm	:1;
    tU08		:2;		/*not used */
    tU08 pllbyp :1;
    tU08		:1;		/*not used */
    tU08 copbyp	:1;
    tU08 rtibyp	:1;
    }bit;
  }tFORBYP;

#define FCM		0x02	/*bit masks	*/
#define PLLBYP	0x10
#define COPBYP	0x40
#define RTIBYP	0x80

typedef struct				
  {
  volatile  tSYNR	synr;	/*synthesizer register */
  volatile  tREFDV	refdv;	/*reference divider register */
  volatile  tREG08	ctflg;	/*clock generator test flags register	*/
  volatile  tCRGFLG	crgflg;	/*clock generator flags register */
  volatile  tCRGINT	crgint;	/*clock generator interrupt control register */
  volatile  tCLKSEL	clksel;	/*clock generator clock select register */
  volatile  tPLLCTL	pllctl;	/*pll control register */
  volatile  tREG08	rtictl;	/*rti control register */
  volatile  tCOPCTL	copctl;	/*cop control register */
  volatile  tFORBYP	forbyp; /*crg force and bypass test register */
  volatile  tREG08	ctctl;	/*crg test control register */
  volatile  tREG08	armcop;	/*cop arming register (to reset write $55:$0AA) */
  }tCRG;

#endif /*S12_CRG_H */