📄 inverter_chain_sizing.m
字号:
% Digital circuit sizing for an inverter chain.% (a figure is generated)%% This is an example taken directly from the paper:%% Digital circuit optimization via geometrical programming % by Boyd, Kim, Patil, and Horowitz% Operations Research 53(6): 899-932, 2005.%% We consider a chain of N inverters driving a load capacitance CL.% The problem is to find optimal scale factors for the inverter% that minimize the sum of them (area), while obeying constraints% on the maximum delay through the circuit, and minimum and maximum% limits on scale factors. There are no limits on the total power.% (For more details about the inverter chain see sec. 2.1.11 in the paper.)%% minimize sum(x) % s.t. T_j <= Dmax for j an output gate% T_j + d_i <= T_i for j in FI(i)% x_min <= x <= x_max%% where variables are x and T.% Here we use data structures and digital circuit models from the% referenced paper.%% Almir Mutapcic 01/26/06clear all; close all;%********************************************************************% problem data%********************************************************************N = 8; % number of invertersCL = 20; % capacitance loadDmax = 20; % maximum delay through the circuitx_min = 1; % minimum scale factorx_max = 20; % maximum scale factor% primary inputs and primary outputs labels (start with N+1)primary_inputs = [N+1];primary_outputs = [N+2];M = N + length( primary_inputs ) + length( primary_outputs );% fan-in cell arrayFI{1} = [N+1];for k = 2:N FI{k} = [k-1];endFI{N+2} = [N];% fan-out cell array (compute it from the fan-in cell array)FO = cell(M,1);for gate = [1:N primary_outputs] preds = FI{gate}; for k = 1:length(preds) FO{preds(k)}(end+1) = gate; endend% input and internal capacitance of gates and the driving resistanceCin_norm = ones(N,1);Cint_norm = ones(N,1);Rdrv_norm = ones(N,1);% place extra capacitance before the input of the 5th inverterCin_norm(5) = 80;% primary output has Cin capacitance (but has no Cload)Cin_po = sparse(M,1);Cin_po(primary_outputs) = CL;% primary input has Cload capacitance (but has no Cin)Cload_pi = sparse(M,1);Cload_pi(primary_inputs) = 1;%********************************************************************% optimization%********************************************************************% optimization variablesgpvar x(N) % sizesgpvar T(N) % arrival times% input capacitance is an affine function of sizesCin = Cin_norm.*x;Cint = Cint_norm.*x;% driving resistance is inversily proportional to sizesR = Rdrv_norm./x;% gate delay is the product of its driving resistance and load cap.Cload = posynomial;for gate = 1:N if ~ismember( FO{gate}, primary_outputs ) Cload(gate) = sum( Cin(FO{gate}) ); else Cload(gate) = Cin_po( FO{gate} ); endendCload = Cload';% delayD = 0.69*ones(N,1).*R.*( Cint + Cload );% create timing constraintstiming_constr = [];for gate = 1:N if ~ismember( FI{gate}, primary_inputs ) for j = FI{gate} % enforce T_j + D_j <= T_i over all gates j that drive i timing_constr = [timing_constr; D(gate) + T(j) <= T(gate)]; end else % enforce D_i <= T_i for gates i connected to primary inputs timing_constr = [timing_constr; D(gate) <= T(gate)]; endend% circuit delay is the max of arrival times for output gatesoutput_gates = [FI{primary_outputs}]; circuit_delay = max( T(output_gates) );% collect all the constraintsconstr = [timing_constr; circuit_delay <= Dmax; x_min*ones(N,1) <= x; x <= x_max*ones(N,1)];% minimize the sum of scale factors subject to above constraints[obj_value, solution, status] = gpsolve(sum(x), constr);assign(solution);% message about extra capacitance and result displaydisp(' ')disp(['Note: there is an extra capacitance between the 4th and 5th inverter'... ' in the chain.'])fprintf(1,'\nOptimal scale factors are: \n'), x% plot scale factors and maximum delay for inverter iclose all;subplot(2,1,1); plot([1:N],T,'g--',[1:N],T,'bo');ylabel('maximum delay T')subplot(2,1,2); stem([1:N],x);ylabel('scale factor x')xlabel('inverter stage')
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -