i960.h

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/* Definitions of target machine for GNU compiler, for Intel 80960
   Copyright (C) 1992, 1993, 1995 Free Software Foundation, Inc.
   Contributed by Steven McGeady, Intel Corp.
   Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
   Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

/* Note that some other tm.h files may include this one and then override
   many of the definitions that relate to assembler syntax.  */

/* Names to predefine in the preprocessor for this target machine.  */
#define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"

/* Name to predefine in the preprocessor for processor variations.  */
#define	CPP_SPEC "%{mic*:-D__i960\
			%{mka:-D__i960KA}%{mkb:-D__i960KB}\
			%{msa:-D__i960SA}%{msb:-D__i960SB}\
			%{mmc:-D__i960MC}\
			%{mca:-D__i960CA}%{mcc:-D__i960CC}\
			%{mcf:-D__i960CF}}\
	%{mka:-D__i960KA__ -D__i960_KA__}\
	%{mkb:-D__i960KB__ -D__i960_KB__}\
	%{msa:-D__i960SA__ -D__i960_SA__}\
	%{msb:-D__i960SB__ -D__i960_SB__}\
	%{mmc:-D__i960MC__ -D__i960_MC__}\
	%{mca:-D__i960CA__ -D__i960_CA__}\
	%{mcc:-D__i960CC__ -D__i960_CC__}\
	%{mcf:-D__i960CF__ -D__i960_CF__}\
	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
		%{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}"

/* -mic* options make characters signed by default.  */
/* Use #if rather than ?: because MIPS C compiler rejects ?: in
   initializers.  */
#if DEFAULT_SIGNED_CHAR
#define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
#else
#define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
#endif

/* Specs for the compiler, to handle processor variations. 
   If the user gives an explicit -gstabs or -gcoff option, then do not
   try to add an implicit one, as this will fail.  */
#define CC1_SPEC \
	"%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mkb}}}}}}}}\
	 %{!gs*:%{!gc*:%{mbout:%{g*:-gstabs}}\
		       %{mcoff:%{g*:-gcoff}}\
		       %{!mbout:%{!mcoff:%{g*:-gstabs}}}}}"

/* Specs for the assembler, to handle processor variations.
   For compatibility with Intel's gnu960 tool chain, pass -A options to
   the assembler.  */
#define ASM_SPEC \
	"%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
	%{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
	%{mlink-relax:-linkrelax}"

/* Specs for the linker, to handle processor variations.
   For compatibility with Intel's gnu960 tool chain, pass -F and -A options
   to the linker.  */
#define LINK_SPEC \
	"%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
	%{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
	%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
	%{mbout:-Fbout}%{mcoff:-Fcoff}\
	%{mlink-relax:-relax}"

/* Specs for the libraries to link with, to handle processor variations.
   Compatible with Intel's gnu960 tool chain.  */
#define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
	  %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"

/* Show we can debug even without a frame pointer.  */
#define CAN_DEBUG_WITHOUT_FP

/* Do leaf procedure and tail call optimizations for -O2 and higher.  */
#define OPTIMIZATION_OPTIONS(LEVEL)		\
{						\
  if ((LEVEL) >= 2)				\
    {						\
      target_flags |= TARGET_FLAG_LEAFPROC;	\
      target_flags |= TARGET_FLAG_TAILCALL;	\
    }						\
}

/* Print subsidiary information on the compiler version in use.  */
#define TARGET_VERSION fprintf (stderr," (intel 80960)");

/* Generate DBX debugging information.  */
#define DBX_DEBUGGING_INFO

/* Generate SDB style debugging information.  */
#define SDB_DEBUGGING_INFO

/* Generate DBX_DEBUGGING_INFO by default.  */
#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG

/* Redefine this to print in hex and adjust values like GNU960.  The extra
   bit is used to handle the type long double.  Gcc does not support long
   double in sdb output, but we do support the non-standard format.  */
#define PUT_SDB_TYPE(A) \
  fprintf (asm_out_file, "\t.type\t0x%x;", (A & 0xf) + 2 * (A & ~0xf))

/* Handle pragmas for compatibility with Intel's compilers.  */
#define HANDLE_PRAGMA(FILE) process_pragma (FILE)

/* Run-time compilation parameters selecting different hardware subsets.  */

/* 960 architecture with floating-point.  */
#define TARGET_FLAG_NUMERICS	0x01
#define TARGET_NUMERICS		(target_flags & TARGET_FLAG_NUMERICS)

/* 960 architecture with memory management.  */
/* ??? Not used currently.  */
#define	TARGET_FLAG_PROTECTED	0x02
#define	TARGET_PROTECTED	(target_flags & TARGET_FLAG_PROTECTED)

/* The following three are mainly used to provide a little sanity checking
   against the -mARCH flags given.  */

/* Nonzero if we should generate code for the KA and similar processors.
   No FPU, no microcode instructions.  */
#define TARGET_FLAG_K_SERIES	0x04
#define TARGET_K_SERIES		(target_flags & TARGET_FLAG_K_SERIES)

/* Nonzero if we should generate code for the MC processor.
   Not really different from KB for our purposes.  */
#define	TARGET_FLAG_MC		0x08
#define TARGET_MC 		(target_flags & TARGET_FLAG_MC)

/* Nonzero if we should generate code for the CA processor.
   Enables different optimization strategies.  */
#define	TARGET_FLAG_C_SERIES	0x10
#define	TARGET_C_SERIES 	(target_flags & TARGET_FLAG_C_SERIES)

/* Nonzero if we should generate leaf-procedures when we find them.
   You may not want to do this because leaf-proc entries are
   slower when not entered via BAL - this would be true when
   a linker not supporting the optimization is used.  */
#define	TARGET_FLAG_LEAFPROC	0x20
#define	TARGET_LEAFPROC		(target_flags & TARGET_FLAG_LEAFPROC)

/* Nonzero if we should perform tail-call optimizations when we find them.
   You may not want to do this because the detection of cases where
   this is not valid is not totally complete.  */
#define	TARGET_FLAG_TAILCALL	0x40
#define	TARGET_TAILCALL		(target_flags & TARGET_FLAG_TAILCALL)

/* Nonzero if use of a complex addressing mode is a win on this implementation.
   Complex addressing modes are probably not worthwhile on the K-series,
   but they definitely are on the C-series.  */
#define	TARGET_FLAG_COMPLEX_ADDR 0x80
#define	TARGET_COMPLEX_ADDR	(target_flags & TARGET_FLAG_COMPLEX_ADDR)

/* Align code to 8 byte boundaries for faster fetching.  */
#define	TARGET_FLAG_CODE_ALIGN	0x100
#define	TARGET_CODE_ALIGN	(target_flags  & TARGET_FLAG_CODE_ALIGN)

/* Append branch prediction suffixes to branch opcodes.  */
/* ??? Not used currently.  */
#define	TARGET_FLAG_BRANCH_PREDICT 0x200
#define	TARGET_BRANCH_PREDICT	(target_flags  & TARGET_FLAG_BRANCH_PREDICT)

/* Forces prototype and return promotions.  */
/* ??? This does not work.  */
#define	TARGET_FLAG_CLEAN_LINKAGE 0x400
#define	TARGET_CLEAN_LINKAGE	(target_flags & TARGET_FLAG_CLEAN_LINKAGE)

/* For compatibility with iC960 v3.0.  */
#define	TARGET_FLAG_IC_COMPAT3_0 0x800 
#define	TARGET_IC_COMPAT3_0	(target_flags & TARGET_FLAG_IC_COMPAT3_0)

/* For compatibility with iC960 v2.0.  */
#define	TARGET_FLAG_IC_COMPAT2_0 0x1000
#define	TARGET_IC_COMPAT2_0	(target_flags & TARGET_FLAG_IC_COMPAT2_0)

/* If no unaligned accesses are to be permitted.  */
#define	TARGET_FLAG_STRICT_ALIGN 0x2000
#define	TARGET_STRICT_ALIGN	(target_flags & TARGET_FLAG_STRICT_ALIGN)

/* For compatibility with iC960 assembler.  */
#define	TARGET_FLAG_ASM_COMPAT	0x4000
#define	TARGET_ASM_COMPAT	(target_flags & TARGET_FLAG_ASM_COMPAT)

/* For compatibility with the gcc960 v1.2 compiler.  Use the old structure
   alignment rules.  Also, turns on STRICT_ALIGNMENT.  */
#define TARGET_FLAG_OLD_ALIGN	0x8000
#define TARGET_OLD_ALIGN	(target_flags & TARGET_FLAG_OLD_ALIGN)

extern int target_flags;

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

/* ??? Not all ten of these architecture variations actually exist, but I
   am not sure which are real and which aren't.  */

#define TARGET_SWITCHES  \
  { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
    {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
			TARGET_FLAG_COMPLEX_ADDR)},\
/*  {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
    {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
    {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
			TARGET_FLAG_COMPLEX_ADDR)},\
/*  {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
    {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
			TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
    {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
			TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
/*  {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
			TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
    {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
			TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
			TARGET_FLAG_CODE_ALIGN)}, */	\
    {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
			TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
    {"numerics", (TARGET_FLAG_NUMERICS)},		\
    {"soft-float", -(TARGET_FLAG_NUMERICS)},		\
    {"leaf-procedures", TARGET_FLAG_LEAFPROC},		\
    {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)},	\
    {"tail-call",TARGET_FLAG_TAILCALL},			\
    {"no-tail-call",-(TARGET_FLAG_TAILCALL)},		\
    {"complex-addr",TARGET_FLAG_COMPLEX_ADDR},		\
    {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)},	\
    {"code-align",TARGET_FLAG_CODE_ALIGN},		\
    {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)},	\
    {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)},	\
    {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)},	\
    {"ic-compat", TARGET_FLAG_IC_COMPAT2_0},		\
    {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0},		\
    {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0},		\
    {"asm-compat",TARGET_FLAG_ASM_COMPAT},		\
    {"intel-asm",TARGET_FLAG_ASM_COMPAT},		\
    {"strict-align", TARGET_FLAG_STRICT_ALIGN},		\
    {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)},	\
    {"old-align", (TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)},	 \
    {"no-old-align", -(TARGET_FLAG_OLD_ALIGN|TARGET_FLAG_STRICT_ALIGN)}, \
    {"link-relax", 0},					\
    {"no-link-relax", 0},				\
    { "", TARGET_DEFAULT}}

/* Override conflicting target switch options.
   Doesn't actually detect if more than one -mARCH option is given, but
   does handle the case of two blatantly conflicting -mARCH options.  */
#define OVERRIDE_OPTIONS					\
{								\
  if (TARGET_K_SERIES && TARGET_C_SERIES)			\
    {								\
      warning ("conflicting architectures defined - using C series", 0); \
      target_flags &= ~TARGET_FLAG_K_SERIES;			\
    }								\
  if (TARGET_K_SERIES && TARGET_MC)				\
    {								\
      warning ("conflicting architectures defined - using K series", 0); \
      target_flags &= ~TARGET_FLAG_MC;				\
    }								\
  if (TARGET_C_SERIES && TARGET_MC)				\
    {								\
      warning ("conflicting architectures defined - using C series", 0);\
      target_flags &= ~TARGET_FLAG_MC;				\
    }								\
  if (TARGET_IC_COMPAT3_0)					\
    {								\
      flag_short_enums = 1;					\
      flag_signed_char = 1;					\
      target_flags |= TARGET_FLAG_CLEAN_LINKAGE;		\
      if (TARGET_IC_COMPAT2_0)					\
	{							\
	  warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
	  target_flags &= ~TARGET_FLAG_IC_COMPAT2_0;		\
	}							\
    }								\
  if (TARGET_IC_COMPAT2_0)					\
    {								\
      flag_signed_char = 1;					\
      target_flags |= TARGET_FLAG_CLEAN_LINKAGE;		\
    }								\
  i960_initialize ();						\
}

/* Don't enable anything by default.  The user is expected to supply a -mARCH
   option.  If none is given, then -mkb is added by CC1_SPEC.  */
#define TARGET_DEFAULT 0

/* Target machine storage layout.  */

/* Define for cross-compilation from a host with a different float format
   or endianness, as well as to support 80 bit long doubles on the i960.  */
#define REAL_ARITHMETIC

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.
   The i960 case be either big endian or little endian.  We only support
   little endian, which is the most common.  */
#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword number is lowest
   numbered.  */
#define WORDS_BIG_ENDIAN 0

/* Number of bits in an addressable storage unit.  */
#define BITS_PER_UNIT 8

/* Bitfields cannot cross word boundaries.  */
#define BITFIELD_NBYTES_LIMITED 1

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 68000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD 32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 4

/* Width in bits of a pointer.  See also the macro `Pmode' defined below.  */
#define POINTER_SIZE 32

/* Width in bits of a long double.  Identical to double for now.  */
#define	LONG_DOUBLE_TYPE_SIZE	64

/* Allocation boundary (in *bits*) for storing pointers in memory.  */
#define POINTER_BOUNDARY 32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY 32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 128

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 128

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 32

/* This makes zero-length anonymous fields lay the next field
   at a word boundary.  It also makes the whole struct have
   at least word alignment if there are any bitfields at all.  */
#define PCC_BITFIELD_TYPE_MATTERS 1

/* Every structure's size must be a multiple of this.  */
#define STRUCTURE_SIZE_BOUNDARY 8

/* No data type wants to be aligned rounder than this.
   Extended precision floats gets 4-word alignment.  */
#define BIGGEST_ALIGNMENT 128

/* Define this if move instructions will actually fail to work
   when given unaligned data.
   80960 will work even with unaligned data, but it is slow.  */
#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN

/* Specify alignment for string literals (which might be higher than the
   base type's minimal alignment requirement.  This allows strings to be
   aligned on word boundaries, and optimizes calls to the str* and mem*