📄 rs6000.h
字号:
/* number of bits in an addressable storage unit */#define BITS_PER_UNIT 8/* Width in bits of a "word", which is the contents of a machine register. Note that this is not necessarily the width of data type `int'; if using 16-bit ints on a 68000, this would still be 32. But on a machine with 16-bit registers, this would be 16. */#define BITS_PER_WORD (TARGET_POWERPC64 ? 64 : 32)#define MAX_BITS_PER_WORD 64/* Width of a word, in units (bytes). */#define UNITS_PER_WORD (TARGET_POWERPC64 ? 8 : 4)#define MIN_UNITS_PER_WORD 4#define UNITS_PER_FP_WORD 8/* Type used for ptrdiff_t, as a string used in a declaration. */#define PTRDIFF_TYPE "int"/* Type used for wchar_t, as a string used in a declaration. */#define WCHAR_TYPE "short unsigned int"/* Width of wchar_t in bits. */#define WCHAR_TYPE_SIZE 16/* A C expression for the size in bits of the type `short' on the target machine. If you don't define this, the default is half a word. (If this would be less than one storage unit, it is rounded up to one unit.) */#define SHORT_TYPE_SIZE 16/* A C expression for the size in bits of the type `int' on the target machine. If you don't define this, the default is one word. */#define INT_TYPE_SIZE (TARGET_64BIT ? 64 : 32)#define MAX_INT_TYPE_SIZE 64/* A C expression for the size in bits of the type `long' on the target machine. If you don't define this, the default is one word. */#define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32)#define MAX_LONG_TYPE_SIZE 64/* A C expression for the size in bits of the type `long long' on the target machine. If you don't define this, the default is two words. */#define LONG_LONG_TYPE_SIZE 64/* A C expression for the size in bits of the type `char' on the target machine. If you don't define this, the default is one quarter of a word. (If this would be less than one storage unit, it is rounded up to one unit.) */#define CHAR_TYPE_SIZE BITS_PER_UNIT/* A C expression for the size in bits of the type `float' on the target machine. If you don't define this, the default is one word. */#define FLOAT_TYPE_SIZE 32/* A C expression for the size in bits of the type `double' on the target machine. If you don't define this, the default is two words. */#define DOUBLE_TYPE_SIZE 64/* A C expression for the size in bits of the type `long double' on the target machine. If you don't define this, the default is two words. */#define LONG_DOUBLE_TYPE_SIZE 64/* Width in bits of a pointer. See also the macro `Pmode' defined below. */#define POINTER_SIZE (TARGET_64BIT ? 64 : 32)/* Allocation boundary (in *bits*) for storing arguments in argument list. */#define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32)/* Boundary (in *bits*) on which stack pointer should be aligned. */#define STACK_BOUNDARY 64/* Allocation boundary (in *bits*) for the code of a function. */#define FUNCTION_BOUNDARY 32/* No data type wants to be aligned rounder than this. */#define BIGGEST_ALIGNMENT (TARGET_64BIT ? 64 : 32)/* Alignment of field after `int : 0' in a structure. */#define EMPTY_FIELD_BOUNDARY 32/* Every structure's size must be a multiple of this. */#define STRUCTURE_SIZE_BOUNDARY 8/* A bitfield declared as `int' forces `int' alignment for the struct. */#define PCC_BITFIELD_TYPE_MATTERS 1/* Make strings word-aligned so strcpy from constants will be faster. */#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))/* Make arrays of chars word-aligned for the same reasons. */#define DATA_ALIGNMENT(TYPE, ALIGN) \ (TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))/* Non-zero if move instructions will actually fail to work when given unaligned data. */#define STRICT_ALIGNMENT 0/* Standard register usage. *//* Number of actual hardware registers. The hardware registers are assigned numbers for the compiler from 0 to just below FIRST_PSEUDO_REGISTER. All registers that the compiler knows about must be given numbers, even those that are not normally considered general registers. RS/6000 has 32 fixed-point registers, 32 floating-point registers, an MQ register, a count register, a link register, and 8 condition register fields, which we view here as separate registers. In addition, the difference between the frame and argument pointers is a function of the number of registers saved, so we need to have a register for AP that will later be eliminated in favor of SP or FP. This is a normal register, but it is fixed. */#define FIRST_PSEUDO_REGISTER 76/* 1 for registers that have pervasive standard uses and are not available for the register allocator. On RS/6000, r1 is used for the stack and r2 is used as the TOC pointer. cr5 is not supposed to be used. On System V implementations, r13 is fixed and not available for use. */#ifndef FIXED_R13#define FIXED_R13 0#endif#define FIXED_REGISTERS \ {0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0}/* 1 for registers not available across function calls. These must include the FIXED_REGISTERS and also any registers that can be used without being saved. The latter must include the registers where values are returned and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. */#define CALL_USED_REGISTERS \ {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1}/* List the order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. We allocate in the following order: fp0 (not saved or used for anything) fp13 - fp2 (not saved; incoming fp arg registers) fp1 (not saved; return value) fp31 - fp14 (saved; order given to save least number) cr1, cr6, cr7 (not saved or special) cr0 (not saved, but used for arithmetic operations) cr2, cr3, cr4 (saved) r0 (not saved; cannot be base reg) r9 (not saved; best for TImode) r11, r10, r8-r4 (not saved; highest used first to make less conflict) r3 (not saved; return value register) r31 - r13 (saved; order given to save least number) r12 (not saved; if used for DImode or DFmode would use r13) mq (not saved; best to use it if we can) ctr (not saved; when we have the choice ctr is better) lr (saved) cr5, r1, r2, ap (fixed) */#define REG_ALLOC_ORDER \ {32, \ 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ 33, \ 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 50, 49, 48, 47, 46, \ 69, 74, 75, 68, 70, 71, 72, \ 0, \ 9, 11, 10, 8, 7, 6, 5, 4, \ 3, \ 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 18, 17, 16, 15, 14, 13, 12, \ 64, 66, 65, \ 73, 1, 2, 67}/* True if register is floating-point. */#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63)/* True if register is a condition register. */#define CR_REGNO_P(N) ((N) >= 68 && (N) <= 75)/* True if register is an integer register. */#define INT_REGNO_P(N) ((N) <= 31 || (N) == 67)/* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. On RS/6000, ordinary registers hold 32 bits worth; a single floating point register holds 64 bits worth. */#define HARD_REGNO_NREGS(REGNO, MODE) \ (FP_REGNO_P (REGNO) \ ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. For POWER and PowerPC, the GPRs can hold any mode, but the float registers only can hold floating modes and DImode, and CR register only can hold CC modes. We cannot put TImode anywhere except general register and it must be able to fit within the register set. */#define HARD_REGNO_MODE_OK(REGNO, MODE) \ (FP_REGNO_P (REGNO) ? \ (GET_MODE_CLASS (MODE) == MODE_FLOAT \ || (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \ : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \ : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \ : 1)/* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, for any hard reg, then this must be 0 for correct output. */#define MODES_TIEABLE_P(MODE1, MODE2) \ (GET_MODE_CLASS (MODE1) == MODE_FLOAT \ ? GET_MODE_CLASS (MODE2) == MODE_FLOAT \ : GET_MODE_CLASS (MODE2) == MODE_FLOAT \ ? GET_MODE_CLASS (MODE1) == MODE_FLOAT \ : GET_MODE_CLASS (MODE1) == MODE_CC \ ? GET_MODE_CLASS (MODE2) == MODE_CC \ : GET_MODE_CLASS (MODE2) == MODE_CC \ ? GET_MODE_CLASS (MODE1) == MODE_CC \ : 1)/* A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2. On the RS/6000, copying between floating-point and fixed-point registers is expensive. */#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \ : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \ : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \ : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \ || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \ || (CLASS1) == LINK_OR_CTR_REGS) \ && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \ || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \ || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \ : 2)/* A C expressions returning the cost of moving data of MODE from a register to or from memory. On the RS/6000, bump this up a bit. */#define MEMORY_MOVE_COST(MODE) \ ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \ ? 3 : 2) \ + 4)/* Specify the cost of a branch insn; roughly the number of extra insns that should be added to avoid a branch. Set this to 3 on the RS/6000 since that is roughly the average cost of an unscheduled conditional branch. */#define BRANCH_COST 3/* A C statement (sans semicolon) to update the integer variable COST based on the relationship between INSN that is dependent on DEP_INSN through the dependence LINK. The default is to make no adjustment to COST. On the RS/6000, ignore the cost of anti- and output-dependencies. In fact, output dependencies on the CR do have a cost, but it is probably not worthwhile to track it. */#define ADJUST_COST(INSN,LINK,DEP_INSN,COST) \ (COST) = rs6000_adjust_cost (INSN,LINK,DEP_INSN,COST)/* Define this macro to change register usage conditional on target flags. Set MQ register fixed (already call_used) if not POWER architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. Conditionally disable FPRs. */#define CONDITIONAL_REGISTER_USAGE \{ \ if (! TARGET_POWER) \ fixed_regs[64] = 1; \ if (TARGET_SOFT_FLOAT) \ for (i = 32; i < 64; i++) \ fixed_regs[i] = call_used_regs[i] = 1; \}/* Specify the registers used for certain standard purposes. The values of these macros are register numbers. *//* RS/6000 pc isn't overloaded on a register that the compiler knows about. *//* #define PC_REGNUM *//* Register to use for pushing function arguments. */#define STACK_POINTER_REGNUM 1/* Base register for access to local variables of the function. */#define FRAME_POINTER_REGNUM 31/* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. This is computed in `reload', in reload1.c. */#define FRAME_POINTER_REQUIRED 0/* Base register for access to arguments of the function. */#define ARG_POINTER_REGNUM 67/* Place to put static chain when calling a function that requires it. */#define STATIC_CHAIN_REGNUM 11
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -