r2000_d-cache.v

这是一个MIPS架构的开发的CPU软核OR2000

	                            cache_data[set_index][entry_index][(`dw*word_offset)+`dw/2	+: `dw/2] = cpu_data_i[15:0];
	                    else							// ls half word
	                            cache_data[set_index][entry_index][(`dw*word_offset) 		+: `dw/2] = cpu_data_i[15:0];
	            width_byte : 
	                    if ((wEndian[1] == 1'b0))	// ms half word 
	                        begin 
	                                if ((wEndian[0] == 1'b0))		// byte 0
	                                        cache_data[set_index][entry_index][(`dw*word_offset)+3*`dw/4 +:`dw/4] = cpu_data_i[7:0];
	                                else							// byte 1
	                                        cache_data[set_index][entry_index][(`dw*word_offset)+2*`dw/4 +:`dw/4] = cpu_data_i[7:0];
	                        end 
	                    else							// ls half word
	                        begin 
	                                if ((wEndian[0] == 1'b0))		// byte 2 
	                                        cache_data[set_index][entry_index][(`dw*word_offset)+`dw/4	+:`dw/4] = cpu_data_i[7:0];
	                                else							// byte 3 
	                                        cache_data[set_index][entry_index][(`dw*word_offset)		+:`dw/4] = cpu_data_i[7:0];
	                        end 
	        endcase
	        
	        if ((write_strategy == copy_back)) 
	                cache_status[set_index][entry_index][`dirty] = `SET;
	
			// if write_through cache, also update main memory
	        if ((write_strategy == write_through)) 
	                do_write_through;
	        else	//  copy_back cache 
	            begin 
	            end
	    end
	endtask
                                               
	// ****************** //
	// Read Hit procedure //
	// ****************** //
	task do_read_hit;
		begin 
			cpu_data_o	<= cache_data[set_index][entry_index][(`dw*word_offset) +: `dw];
		end
	endtask
                                               
	// ******************** //
	// Write Miss procedure //
	// ******************** //
	task do_write_miss;
		begin 
			// if write_through cache, just update main memory
			if ((write_strategy == write_through)) 
				do_write_through;
			else begin	//  copy_back cache 
				replace_line;
				if ((rst_i == `SET)) 
					disable do_write_miss;
				do_write_hit;
			end
		end
	endtask
                                               
	// ******************* //
	// Read Miss procedure //
	// ******************* //
	task do_read_miss;
		begin 
			replace_line;
			if ((rst_i == `SET)) 
				disable do_read_miss;
			do_read_hit;
		end
	endtask
                                               
	task do_write_through;
	    begin 
	
			wb_wr1(cpu_addr_i, 4'hf, cpu_data_i);
	        rCpuReady	<= #(tpd_clk_out) `SET;//mem_ready;
	        
//			@(`CLOCK_REVER clk_i );
			@(`CLOCK_EDGE clk_i );
	        
	        rCpuReady	<= #(tpd_clk_out) `CLEAR;
	    end
	endtask
                                               
	task replace_line;
	    begin
	    	//  first chose an entry using "random" number generator 
	        entry_index = next_replacement_entry_index;
	        next_replacement_entry_index = ((next_replacement_entry_index + 1) % associativity);
	        
			if (cache_status[set_index][entry_index][`dirty]) 
				copy_back_line;
			fetch_line;
	    end
	endtask
                                               
	task copy_back_line;
	    
	    integer next_address;
	    integer old_word_offset;
	
	    begin 
	        next_address = (((cache_status[set_index][entry_index][`tag] * number_of_sets) + set_index) * line_size);
			wb_wr_mult(next_address, 4'hf, 0, words_per_line);
	        cache_status[set_index][entry_index][`dirty] = `CLEAR;
	    end
	endtask

	task fetch_line;
	    
	    integer next_address;
	    integer new_word_offset;
	
	    begin 
	        next_address = ((cpu_address / line_size) * line_size);
			wb_rd_mult(next_address, 4'hf, 0 ,words_per_line);
	        
	        cache_status[set_index][entry_index][`dirty]	= `CLEAR;
	        cache_status[set_index][entry_index][`valid]	= `SET;
	        cache_status[set_index][entry_index][`tag]		= cpu_tag;
	        
	    end
	endtask
                                                   
	/*======================================================================================================================================================*/
	/*	WishBone compatible bus functions						*/
	/*======================================================================================================================================================*/
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
	task wb_wr1;
	input	[`aw-1:0]	a;
	input	[`slw-1:0]	s;
	input	[`dw-1:0]	d;
	
		begin
		
			@(`CLOCK_EDGE clk_i);
			#1;
			ADR_O		= a;
			DAT_O		= d;
			CYC_O		= 1;
			STB_O		= 1;
			WE_O		= 1;
			SEL_O		= s;
			
			@(`CLOCK_EDGE clk_i);
			while(~ACK_I & ~ERR_I)	@(`CLOCK_EDGE clk_i);
			#1;
			CYC_O		= 0;
			STB_O		= 0;
			ADR_O		= 32'hxxxx_xxxx;
			DAT_O		= 32'hxxxx_xxxx;
			WE_O		= 1'hx;
			SEL_O		= 4'hx;
		
		end
	endtask

////////////////////////////////////////////////////////////////////
//
// Write multi Word Task
//
	task wb_wr_mult;
	input	[`aw-1:0]	a;
	input	[`slw-1:0]	s;
	input				delay;
	input				count;
	
	integer				delay;
	integer				count;
	integer				n;
	
		begin
		
			@(`CLOCK_EDGE clk_i);
			#1;
			CYC_O = 1;
			
			for(n=0;n<count;n=n+1) begin
				repeat(delay) begin
					@(`CLOCK_EDGE clk_i);
					#1;
				end
				ADR_O		= a + (n*4);
				//DAT_O		= wr_mem[n + wr_cnt];
				DAT_O		= cache_data[set_index][entry_index][(`dw*n) +: `dw];
				STB_O		= 1;
				WE_O		= 1;
				SEL_O		= s;
				if(n!=0)	@(`CLOCK_EDGE clk_i);
				while(~ACK_I & ~ERR_I)	@(`CLOCK_EDGE clk_i);
				#2;
				STB_O		= 0;
				WE_O		= 1'bx;
				SEL_O		= 4'hx;
				DAT_O		= 32'hxxxx_xxxx;
				ADR_O		= 32'hxxxx_xxxx;
			end
			
			CYC_O=0;
			ADR_O = 32'hxxxx_xxxx;
			
			wr_cnt = wr_cnt + count;
		end
	endtask

////////////////////////////////////////////////////////////////////
//
// Read multi Word Task
//
	task wb_rd_mult;
	input	[`aw-1:0]	a;
	input	[`slw-1:0]	s;
	input		delay;
	input		count;
	
	integer		delay;
	integer		count;
	integer		n;
	
		begin
		
			@(`CLOCK_EDGE clk_i);
			#1;
			CYC_O = 1;
			WE_O = 0;
			SEL_O = s;
			repeat(delay)	@(`CLOCK_EDGE clk_i);
			
			for(n=0;n<count-1;n=n+1)begin
				ADR_O = a + (n*4);
				STB_O = 1;
				while(~ACK_I & ~ERR_I)	@(`CLOCK_EDGE clk_i);
				//rd_mem[n + rd_cnt] = DAT_I;
				cache_data[set_index][entry_index][(`dw*n) +: `dw] = DAT_I;
				#2;
				STB_O=0;
				WE_O = 1'hx;
				SEL_O = 4'hx;
				ADR_O = 32'hxxxx_xxxx;
				repeat(delay)begin
					@(`CLOCK_EDGE clk_i);
					#1;
				end
				WE_O = 0;
				SEL_O = s;
			end
			
			ADR_O = a+(n*4);
			STB_O = 1;
			@(`CLOCK_EDGE clk_i);
			while(~ACK_I & ~ERR_I)	@(`CLOCK_EDGE clk_i);
			//rd_mem[n + rd_cnt] = DAT_I;
			cache_data[set_index][entry_index][(`dw*n) +: `dw] = DAT_I;
			#1;
			STB_O=0;
			CYC_O=0;
			WE_O = 1'hx;
			SEL_O = 4'hx;
			ADR_O = 32'hxxxx_xxxx;
			
			rd_cnt = rd_cnt + count;
		end
	endtask

endmodule
//////////////////////////////////////////////////////////////////////////