wavelet_lifting_pld.tan.qmsg

小波提升Verilog代码

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "pre2_odd_reg\[17\] y11\[18\] clk 3.8 ns " "Info: Found hold time violation between source  pin or register \"pre2_odd_reg\[17\]\" and destination pin or register \"y11\[18\]\" for clock \"clk\" (Hold time is 3.8 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "10.000 ns + Largest " "Info: + Largest clock skew is 10.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_91 193 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_91; Fanout = 193; CLK Node = 'clk'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.800 ns) 3.600 ns oe~reg0 2 REG LC1_T52 131 " "Info: 2: + IC(1.200 ns) + CELL(0.800 ns) = 3.600 ns; Loc. = LC1_T52; Fanout = 131; REG Node = 'oe~reg0'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clk oe~reg0 } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(9.200 ns) + CELL(0.000 ns) 12.800 ns y11\[18\] 3 REG LC1_U41 4 " "Info: 3: + IC(9.200 ns) + CELL(0.000 ns) = 12.800 ns; Loc. = LC1_U41; Fanout = 4; REG Node = 'y11\[18\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "9.200 ns" { oe~reg0 y11[18] } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.400 ns ( 18.75 % ) " "Info: Total cell delay = 2.400 ns ( 18.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.400 ns ( 81.25 % ) " "Info: Total interconnect delay = 10.400 ns ( 81.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "12.800 ns" { clk oe~reg0 y11[18] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "12.800 ns" { clk clk~out oe~reg0 y11[18] } { 0.000ns 0.000ns 1.200ns 9.200ns } { 0.000ns 1.600ns 0.800ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.800 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 1.600 ns clk 1 CLK PIN_91 193 " "Info: 1: + IC(0.000 ns) + CELL(1.600 ns) = 1.600 ns; Loc. = PIN_91; Fanout = 193; CLK Node = 'clk'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.000 ns) 2.800 ns pre2_odd_reg\[17\] 2 REG LC6_U51 2 " "Info: 2: + IC(1.200 ns) + CELL(0.000 ns) = 2.800 ns; Loc. = LC6_U51; Fanout = 2; REG Node = 'pre2_odd_reg\[17\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.200 ns" { clk pre2_odd_reg[17] } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 57.14 % ) " "Info: Total cell delay = 1.600 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 42.86 % ) " "Info: Total interconnect delay = 1.200 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.800 ns" { clk pre2_odd_reg[17] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.800 ns" { clk clk~out pre2_odd_reg[17] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 1.600ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "12.800 ns" { clk oe~reg0 y11[18] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "12.800 ns" { clk clk~out oe~reg0 y11[18] } { 0.000ns 0.000ns 1.200ns 9.200ns } { 0.000ns 1.600ns 0.800ns 0.000ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.800 ns" { clk pre2_odd_reg[17] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.800 ns" { clk clk~out pre2_odd_reg[17] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 1.600ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.800 ns - " "Info: - Micro clock to output delay of source is 0.800 ns" {  } { { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 49 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.900 ns - Shortest register register " "Info: - Shortest register to register delay is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pre2_odd_reg\[17\] 1 REG LC6_U51 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_U51; Fanout = 2; REG Node = 'pre2_odd_reg\[17\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { pre2_odd_reg[17] } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.600 ns) 2.500 ns lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\] 2 COMB LC2_U32 2 " "Info: 2: + IC(1.900 ns) + CELL(0.600 ns) = 2.500 ns; Loc. = LC2_U32; Fanout = 2; COMB Node = 'lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.500 ns" { pre2_odd_reg[17] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[18] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/quartus ii/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 3.900 ns lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[19\] 3 COMB LC3_U32 1 " "Info: 3: + IC(0.000 ns) + CELL(1.400 ns) = 3.900 ns; Loc. = LC3_U32; Fanout = 1; COMB Node = 'lpm_add_sub:Add1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[19\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "1.400 ns" { lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/quartus ii/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.200 ns) 6.900 ns y11\[18\] 4 REG LC1_U41 4 " "Info: 4: + IC(1.800 ns) + CELL(1.200 ns) = 6.900 ns; Loc. = LC1_U41; Fanout = 4; REG Node = 'y11\[18\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "3.000 ns" { lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] y11[18] } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 46.38 % ) " "Info: Total cell delay = 3.200 ns ( 46.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.700 ns ( 53.62 % ) " "Info: Total interconnect delay = 3.700 ns ( 53.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.900 ns" { pre2_odd_reg[17] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] y11[18] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "6.900 ns" { pre2_odd_reg[17] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] y11[18] } { 0.000ns 1.900ns 0.000ns 1.800ns } { 0.000ns 0.600ns 1.400ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.500 ns + " "Info: + Micro hold delay of destination is 1.500 ns" {  } { { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 59 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "12.800 ns" { clk oe~reg0 y11[18] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "12.800 ns" { clk clk~out oe~reg0 y11[18] } { 0.000ns 0.000ns 1.200ns 9.200ns } { 0.000ns 1.600ns 0.800ns 0.000ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "2.800 ns" { clk pre2_odd_reg[17] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "2.800 ns" { clk clk~out pre2_odd_reg[17] } { 0.000ns 0.000ns 1.200ns } { 0.000ns 1.600ns 0.000ns } } } { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "6.900 ns" { pre2_odd_reg[17] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] y11[18] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "6.900 ns" { pre2_odd_reg[17] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:Add1|addcore:adder|a_csnbuffer:result_node|cs_buffer[19] y11[18] } { 0.000ns 1.900ns 0.000ns 1.800ns } { 0.000ns 0.600ns 1.400ns 1.200ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "even_reg\[26\] s\[26\] clk 8.200 ns register " "Info: tsu for register \"even_reg\[26\]\" (data pin = \"s\[26\]\", clock pin = \"clk\") is 8.200 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.300 ns + Longest pin register " "Info: + Longest pin to register delay is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.400 ns) 2.400 ns s\[26\] 1 PIN PIN_235 2 " "Info: 1: + IC(0.000 ns) + CELL(2.400 ns) = 2.400 ns; Loc. = PIN_235; Fanout = 2; PIN Node = 's\[26\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "" { s[26] } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.700 ns) + CELL(1.200 ns) 10.300 ns even_reg\[26\] 2 REG LC5_U36 3 " "Info: 2: + IC(6.700 ns) + CELL(1.200 ns) = 10.300 ns; Loc. = LC5_U36; Fanout = 3; REG Node = 'even_reg\[26\]'" {  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "7.900 ns" { s[26] even_reg[26] } "NODE_NAME" } } { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.600 ns ( 34.95 % ) " "Info: Total cell delay = 3.600 ns ( 34.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 65.05 % ) " "Info: Total interconnect delay = 6.700 ns ( 65.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus ii/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus ii/win/TimingClosureFloorplan.fld" "" "10.300 ns" { s[26] even_reg[26] } "NODE_NAME" } } { "d:/quartus ii/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus ii/win/Technology_Viewer.qrui" "10.300 ns" { s[26] s[26]~out even_reg[26] } { 0.000ns 0.000ns 6.700ns } { 0.000ns 2.400ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "wavelet_lifting_pld.v" "" { Text "F:/myprojects/wavelet_lifting_pld/wavelet_lifting_pld.v" 49 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination